AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 334

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

30.8
30.8.1
30.8.2
30.8.2.1
30.8.2.2
Multi-master Mode
More than one master may handle the bus at the same time without data corruption by using arbitration.
Arbitration starts as soon as two or more masters place information on the bus at the same time, and stops (arbitra-
tion is lost) for the master that intends to send a logical one while the other master sends a logical zero.
As soon as arbitration is lost by a master, it stops sending data and listens to the bus in order to detect a stop.
When the stop is detected, the master who has lost arbitration may put its data on the bus by respecting arbitration.
Arbitration is illustrated in
Two multi-master modes may be distinguished:
Note:
In this mode, TWI is considered as a Master only (MSEN is always at one) and must be driven like a Master with
the ARBLST (ARBitration Lost) flag in addition.
If arbitration is lost (ARBLST = 1), the programmer must reinitiate the data transfer.
If the user starts a transfer (ex.: DADR + START + W + Write in THR) and if the bus is busy, the TWI automatically
waits for a STOP condition on the bus to initiate the transfer (see
Note:
The automatic reversal from Master to Slave is not supported in case of a lost arbitration.
Then, in the case where TWI may be either a Master or a Slave, the programmer must manage the pseudo Multi-
master mode described in the steps below.
Note:
1. TWI is considered as a Master only and will never be addressed.
2. TWI may be either a Master or a Slave and may be addressed.
1. Program TWI in Slave mode (SADR + MSDIS + SVEN) and perform Slave Access (if TWI is addressed).
2. If TWI has to be set in Master mode, wait until TXCOMP flag is at 1.
3. Program Master mode (DADR + SVDIS + MSEN) and start the transfer (ex: START + Write in THR).
4. As soon as the Master mode is enabled, TWI scans the bus in order to detect if it is busy or free. When the
5. As soon as the transfer is initiated and until a STOP condition is sent, the arbitration becomes relevant
6. If the arbitration is lost (ARBLST is set to 1), the user must program the TWI in Slave mode in the case
7. If TWI has to be set in Slave mode, wait until TXCOMP flag is at 1 and then program the Slave mode.
Definition
Different Multi-master Modes
TWI as Master Only
TWI as Master or Slave
bus is considered as free, TWI initiates the transfer.
and the user must monitor the ARBLST flag.
where the Master that won the arbitration wanted to access the TWI.
In both Multi-master modes arbitration is supported.
The state of the bus (busy or free) is not indicated in the user interface.
In the case where the arbitration is lost and TWI is addressed, TWI will not acknowledge even if it is programmed in
Slave mode as soon as ARBLST is set to 1. Then, the Master must repeat SADR.
Figure 30-21 on page
335.
Figure 30-20 on page
SAM7S Series [DATASHEET]
335).
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