AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 370
AT91SAM7S256D-AU
Manufacturer Part Number
AT91SAM7S256D-AU
Description
ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
Manufacturer
Atmel
Series
SAM7S256r
Datasheet
1.AT91SAM7S256D-AU.pdf
(775 pages)
Specifications of AT91SAM7S256D-AU
Rohs
yes
Core
ARM
Processor Series
AT91SAM
Data Bus Width
16 bit/32 bit
Maximum Clock Frequency
55 MHz
Program Memory Size
256 KB
Data Ram Size
64 KB
On-chip Adc
Yes
Operating Supply Voltage
3 V to 3.6 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
LQFP-64
Mounting Style
SMD/SMT
Interface Type
2-Wire, I2S, SPI, USART
Length
7 mm
Available stocks
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Price
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Part Number:
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31.6.3.2
Figure 31-9. Transmitter Status
If the USART is programmed in asynchronous operating mode (SYNC = 0), the receiver oversamples the RXD
input line. The oversampling is either 16 or 8 times the Baud Rate clock, depending on the OVER bit in the Mode
Register (US_MR).
The receiver samples the RXD line. If the line is sampled during one half of a bit time at 0, a start bit is detected
and data, parity and stop bits are successively sampled on the bit rate clock.
If the oversampling is 16, (OVER at 0), a start is detected at the eighth sample at 0. Then, data bits, parity bit and
stop bit are sampled on each 16 sampling clock cycle. If the oversampling is 8 (OVER at 1), a start bit is detected
at the fourth sample at 0. Then, data bits, parity bit and stop bit are sampled on each 8 sampling clock cycle.
The number of data bits, first bit sent and parity mode are selected by the same fields and bits as the transmitter,
i.e. respectively CHRL, MODE9, MSBF and PAR. For the synchronization mechanism only, the number of stop
bits has no effect on the receiver as it considers only one stop bit, regardless of the field NBSTOP, so that resyn-
chronization between the receiver and the transmitter can occur. Moreover, as soon as the stop bit is sampled, the
receiver starts looking for a new start bit so that resynchronization can also be accomplished when the transmitter
is operating with one stop bit.
Figure 31-10
chronous mode.
Asynchronous Receiver
Baud Rate
TXEMPTY
and
US_THR
TXRDY
Clock
Write
TXD
Figure 31-11
Start
Bit
D0
illustrate start detection and character reception when USART operates in asyn-
D1
D2
D3
D4
D5
D6
D7
Parity
Bit
Stop
Bit
Start
Bit
D0
D1
D2
SAM7S Series [DATASHEET]
D3
D4
D5
D6
D7
6175M–ATARM–26-Oct-12
Parity
Bit
Stop
Bit
370
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