HW-V5-PCIE2-UNI-G Xilinx Inc, HW-V5-PCIE2-UNI-G Datasheet - Page 25

• Manufacturer Part Number: HW-V5-PCIE2-UNI-G
• Description: KIT DEV PCIEXPRESS GTX VIRTEX5
• Manufacturer: Xilinx Inc
• Series: Virtex™ -5r
• Type: FPGAr

Specifications of HW-V5-PCIE2-UNI-G

• Contents: Board, CD
• For Use With/related Products: Virtex™-5 FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Virtex-5 FPGA ML555 Development Kit
UG201 (v1.4) March 10, 2008
R
Table 3-1: P13 Edge Connector Socket Pinout for PCI Express Designs (Continued)
The PCI Express Card Electromechanical Specification requires add-in cards to implement
variable-length edge finger pads and tie PRSNT1_B and PRSNT2_B signals together on the
Notes:
1. PCIE_PRSNT1_B can be connected to one of three PCIE_PRSNT2_B signals by connecting a shunt on
2. No connect on the ML555 board.
3. The ML555 board layout provides two methods of interfacing the PCIE_REFCLK to the FPGA. The
4. The PETPX and PETNX pins connect to the PCI Express transmitter differential pair on the system
5. The PERPX and PERNX pins connect to the PCI Express receiver differential pair on the system board
6. PCIE_PERST connects to FPGA pin AE14.
connector P45. See
default method is to AC couple the 100 MHz PCIE_REFCLK directly to the GTP_DUAL tile X0Y2
MGTREFCLK input pins. An alternative method is to remove two 0Ω resistors and install an
ICS874003-02 PCI Express Jitter attenuator module, which provides a 100, 125, or 250 MHz reference
clock to the GTP transceiver. The jitter attentuator has two LVDS outputs that connect to the GTP and
FPGA global clock inputs. One of the jitter attentuator LVDS outputs is connected to the MGTREFCLK
inputs of GTP_DUAL tile X0Y2 for PCI Express lanes 0 and 1. The PCIE_REFCLK is also connected to
the FPGA global clock network on pins J16 and J17. Internal FPGA clock buffers distribute this clock to
other GTP_DUAL tiles for PCI Express operation. The architecture of the FPGA permits an external
MGTREFCLK to be driven a maximum of three GTP_DUAL tiles up or down. See
with Optional ICS874003-02 Clock Jitter Attenuator (PCI Express Operation),” page 60
information.
board and the PCI Express receiver on the add-in card.
and the PCI Express transmitter on the add-in card.
P13 A Side
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
Table 3-2
www.xilinx.com
RESERVED
RESERVED
for application information.
PERN3
PERN4
PERN5
PERN6
PERN7
Signal
PERP4
PERP5
PERP6
PERP7
GND
GND
GND
GND
GND
GND
GND
GND
GND
Edge Connector for PCI Express Operation
P13 B Side
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
PCIE_PRSNT2_B
PCIE_PRSNT2_B
“Serial Bus Clocking
RESERVED
PETN4
PETN5
PETN6
PETN7
Signal
PETP4
PETP5
PETP6
PETP7
GND
GND
GND
GND
GND
GND
GND
GND
GND
for additional
(1)
(1)
25