HW-V5-PCIE2-UNI-G Xilinx Inc, HW-V5-PCIE2-UNI-G Datasheet - Page 69

• Manufacturer Part Number: HW-V5-PCIE2-UNI-G
• Description: KIT DEV PCIEXPRESS GTX VIRTEX5
• Manufacturer: Xilinx Inc
• Series: Virtex™ -5r
• Type: FPGAr

Specifications of HW-V5-PCIE2-UNI-G

• Contents: Board, CD
• For Use With/related Products: Virtex™-5 FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 3-25: FPGA Signals for Serial Programming of the Clock Synthesizer Modules (Continued)
Virtex-5 FPGA ML555 Development Kit
UG201 (v1.4) March 10, 2008
Notes:
1. These FPGA output signals are connected to FPGA bank 13. The reference voltage, V
2. The LVDSCLKMOD_2 differential clock is connected to a differential clock multiplexer. The output of the multiplexer goes to FPGA
LVDSCLKMOD1_P
LVDSCLOCKMOD1_N
MGT_X0Y1_RCLKP
MGT_X0Y1_RCLKN
PLOAD_2
STROBE_2
SDATA_2
SCLOCK_2
LVDSCLKMOD2_P
LVDSCLKMOD2_N
MGT_X0Y0_RCLKP
MGT_X0Y0_RCLKN
schematics on the CD-ROM for additional information. The clock synthesizer clocks are not connected to FPGA bank 13.
global clock inputs J20(P) and J21(N) and MGT_X0Y5 MGTREFCLK inputs E4 and D4.
Signal
R
(2)
(2)
Clock Synthesizer 1 clock outputs. See
representation of the clock network on the ML555 board.
ICS8442 parallel load input used for parallel loading of
multiplier and divider switch inputs to the device. A
pushbutton switch is provided on the ML555 board to permit
the user to load the settings into the synthesizer. This signal is
asserted to perform a parallel load operation. For serial
configuration of the ICS8442, this signal should always be
deasserted (inactive).
ICS8442 serial load input used to load serialized multiplier and
divisor constants into the ICS8442. Asserted to perform serial to
parallel loading for user-defined clock synthesis. This signal
should be deasserted during the serial data clocking, asserted,
and then deasserted for one clock cycle to complete the serial to
parallel loading of the data into the device.
This signal contains the ICS8442 serial data input. The serial
data is provided in the sequence T1, T0, NULL, N1, N0, M8, M7,
M6, M5, M4, M3, M2, M1, and finally M0. The ICS8442 data
sheet provides a serial loading timing diagram and definitions
for serial data bits.
The ICS8442 serial clock input should only be active during
serial loading of the synthesizer. The clock should be deasserted
at all other times. Data is clocked into the ICS8442 on the rising
edge of the SCLOCK. The ICS8442 data sheet provides a serial
loading timing diagram and definitions for serial data bits.
The Clock Synthesizer 2 clock outputs go through clock
multiplexer U3, which connects to the FPGA global clock and
the GTP REFCLK inputs. See
representation of the clock network on the ML555 board.
www.xilinx.com
Description
Figure 3-8
Figure 3-8
for a schematic
for a schematic
CCO
, for this bank is 3.0V. See the ML555 board
FPGA Pin
J21, D4
J20, E4
AM33
AK32
AL34
AJ32
H19
H20
AF4
AF3
AL5
AL4
Clock Generation
(1)
Output
Output
Output
Output
In/Out
FPGA
Input
Input
Input
Input
Input
Input
Input
Input
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