HW-V5-PCIE2-UNI-G Xilinx Inc, HW-V5-PCIE2-UNI-G Datasheet - Page 58

• Manufacturer Part Number: HW-V5-PCIE2-UNI-G
• Description: KIT DEV PCIEXPRESS GTX VIRTEX5
• Manufacturer: Xilinx Inc
• Series: Virtex™ -5r
• Type: FPGAr

Specifications of HW-V5-PCIE2-UNI-G

• Contents: Board, CD
• For Use With/related Products: Virtex™-5 FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 3: Hardware Description
Table 3-19: FPGA Global Clock Inputs (Continued)
Table 3-20: GTP Reference Clock Inputs
58
Notes:
1. AC coupled.
2. The SMA clock input can be differential or single ended. When driven with a single ended clock source, connector J10 should be
3. Single-ended clock input. All other clocks are differential inputs.
4. Control output port SATA_MGT_CLKSEL on FPGA pin H15:
5. The SMA GCLK ports can be used as outputs to route internal single-ended or differential signals to an oscilloscope for debugging
Notes:
1. GTP REFCLK input pins are listed as differential pairs, MGTREFCLKP and MGTREFCLKN, respectively.
2. Signal names for differential clocking have P/N designators at the end to indicate positive or negative input/output of the
3. The transceivers can still be utilized using internal clock routing resources, either global or GTP clock buffering. See the Virtex-5
4. Clock Synthesizer 1 is typically utilized to generate the clock for the DDR2 memory.
5. The GTP transceivers can also be clocked using the differential SMA clock inputs, J10 and J11, connected to the global clock inputs.
6. These GTP transceivers are connected to the PCI Express connector J13. The ML555 board supports x1, x4, and x8 lane endpoint PCI
7. The 100 MHz differential PCI Express system board spread spectrum clock input goes to GTP MGTREFCLK inputs Y4 and Y3. For
K18, K19, H13 No connects
Designator
GTP LOC
FPGA Pins
used to input the clock to the FPGA. Differential clock inputs to the FPGA should use the IBUFDS input buffer library primitive.
Setting the DIFF_TERM attribute of the IBUFDS to TRUE provides 100 Ω on-chip termination for the LVDS clock source driver.
(= 0) selects the fixed 125 MHz oscillator output
(= 1) selects the variable-frequency Clock Synthesizer 2 output
as the clock source for the differential global clock inputs on FPGA pins J20 and J21.
ML555 designs.
differential clock receiver. See the ML555 board schematics and the ML555 FPGA design constraint file on the CD-ROM for
additional information.
FPGA RocketIO GTP Transceiver User Guide for additional information on GTP clocking.
Express applications. ES silicon requires specific GTP_DUAL tile connections for 8-lane PCI Express Endpoint applications.
Production silicon does not have these restrictions.
multilane PCI Express designs, internal dedicated clock routing resources are used to distribute the PCI Express system clock to
GTP_DUAL tiles X0Y0, X0Y1, and X0Y3. See
Operation),” page 60
X0Y0
X0Y1
X0Y2
X0Y3
X0Y4
X0Y5
(6)
(6)
(6)
(6)
GTP Reference Clock Inputs
FPGA Pins
AL5, AL4
AF4, AF3
H4, H3
E4, D4
Y4, Y3
P4, P3
for additional information.
Signal Name
All GTP REFCLK inputs have clock inputs routed to them.
designators, FPGA pins, and clock sources that drive the reference clock inputs of the GTP
transceivers. The lanes are for PCI Express applications.
(1)
MGT_X0Y0_REFCLK
MGT_X0Y1_REFCLK
PCIE_REFCLK
SMA_GTPCLK
SFP_MGT_REFCLK
SATA_MGT_REFCLK Selectable: 125 MHz Oscillator or
Signal Name
“Serial Bus Clocking with Optional ICS874003-02 Clock Jitter Attenuator (PCI Express
Unused global clock inputs to FPGA
(7)
(2)
www.xilinx.com
Clock Synthesizer 2
Clock Synthesizer 1
Spread spectrum clock input from
PCI Express system unit connector
P13. Pins A13 (P) and A14 (N).
SMA connectors P12 (P) and P13 (N) Lanes 4 and 5
125 MHz Oscillator
Clock Synthesizer 2
Clock Source
Clock Source
(3,4,5)
Virtex-5 FPGA ML555 Development Kit
Table 3-20
UG201 (v1.4) March 10, 2008
Lanes 6 and 7
Lanes 2 and 3
Lanes 0 and 1
SATA and SMA interfaces
SFP1 and SFP2 interfaces
Application Usage
shows GTP location
R