HW-V5-PCIE2-UNI-G Xilinx Inc, HW-V5-PCIE2-UNI-G Datasheet - Page 82

• Manufacturer Part Number: HW-V5-PCIE2-UNI-G
• Description: KIT DEV PCIEXPRESS GTX VIRTEX5
• Manufacturer: Xilinx Inc
• Series: Virtex™ -5r
• Type: FPGAr

Specifications of HW-V5-PCIE2-UNI-G

• Contents: Board, CD
• For Use With/related Products: Virtex™-5 FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 3: Hardware Description
82
GTP Transceiver Power
DDR2 SODIMM Power
Power Supply Monitoring
Three low drop-out (LDO) voltage regulators are provided for the analog voltage inputs to
the GTP transceivers. Each regulator has a voltage divider circuit that permits the voltage
to be adjusted, if required, simply by changing resistance value of the voltage divider. Each
regulator can source up to 4A of current. A single voltage regulator sources power to the
AVTTX, AVTRX, and VVTTRXC inputs of the GTP transceivers. The ML555 board does
not provide separate power supplies for the transmitter and receiver termination voltages.
The GTP transceiver analog power supplies are filtered in accordance with the Virtex-5
FPGA RocketIO GTP Transceiver User Guide. Eight of the 12 GTPs on the ML555 board are
specifically targeted solely for PCI Express applications.
Power consumption for the DDR2 memory interface is dependent upon the density and
speed of the memory installed in the SODIMM socket.
current consumption requirements by density and transfer rate for Micron Semiconductor
SODIMMs supported by the ML555 board. Memory data sheet specifications should be
consulted to determine specific power requirements for the SODIMM devices.
Higher densities and higher performance SODIMMs are supported, however, the user
must calculate total application power and stay within the PCI and or PCI Express add-in
card specifications.
Table 3-35: DDR2 SODIMM Current Consumption versus Data Transfer Rate
Current consumption can be even higher than shown in
banks are interleaved in the DDR2 memory. Interleaving is accomplished by using the
BA[2:0] bank address as the least-significant column address bits to the DDR2 memory.
While interleaving does not increase memory performance, it increases power dissipation
and should be avoided for PCI Express and PCI bus applications where add-in card power
is limited by specification to 25W.
The ML555 board provides capabilities to monitor and measure the voltage and current for
the FPGA internal voltage and all analog GTP voltage regulators.
block diagram of the voltage sensing circuit. Only those supplies central to PCI Express
power functions are provided with power supply monitoring capabilities. A 10 mΩ Kelvin
resistor is placed in series between the regulated output and the load on the board. The
input and output port of the series resistor is routed to a header that can be connected to a
Volt-Ohm-Meter (VOM) to measure the voltage drop across the resistor. The current then
can be calculated dividing the voltage by 0.010Ω. Power equals voltage times current.
Memory Density
128 MB
256 MB
512 MB
www.xilinx.com
400 MT/s
480 mA
620 mA
720 mA
533 MT/s
720 mA
780 mA
780 mA
Virtex-5 FPGA ML555 Development Kit
Table 3-35
Table 3-35
UG201 (v1.4) March 10, 2008
shows approximate 1.8V
Figure 3-17
if the four memory
667 MT/s
1100 mA
860 mA
940 mA
shows a
R