HW-V5-PCIE2-UNI-G Xilinx Inc, HW-V5-PCIE2-UNI-G Datasheet - Page 4

• Manufacturer Part Number: HW-V5-PCIE2-UNI-G
• Description: KIT DEV PCIEXPRESS GTX VIRTEX5
• Manufacturer: Xilinx Inc
• Series: Virtex™ -5r
• Type: FPGAr

Specifications of HW-V5-PCIE2-UNI-G

• Contents: Board, CD
• For Use With/related Products: Virtex™-5 FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Virtex-5 FPGA ML555 Development Kit
03/10/08
Date
Version
1.4
Added additional reference documents and application notes in
Documentation,” page
ML555 Development Kit,” page
including removal of Virtex-5 LogiCORE Endpoint Block Wrapper. Included Platform
USB Programming Cable and ISE Evaluation Software in
Specified 30 MHz LVCMOS oscillator as one of three on board clock sources in
Board,” page
oscillator. Added reference and link to Xilinx application notes XAPP1022 and
XAPP1002 in
to
to
PCI and PCI-X Operation,” page
notes XAPP858 and XAPP865 in
pin assignments for IIC_SDA_SFP{1/2} and IIC_SCK_SFP{1/2} signals and updated
footnotes 2 and 5 in
XAPP870 in
P1_RCLK1 signal in
Laboratories VCP device drivers in the
oscillator frequency for component Y2 in
FPGA GCLK input pin L19 to FPGA_GCLK_30MHZ in
page
to FPGA_GCLK_30MHZ in
Updated footnote 3 in
of the ML555. Changed CPLD CLK to 30 MHz in
and
30 MHz in
configuration frequency recommendation. Added BitGen command sequence to
demonstrate selection of 20 MHz CCLK configuration clock in
Generation and Programming,” page
Table 3-1, page 24
Table 3-3, page
Figure 4-7, page 99
56, and
Figure 4-8, page
“Serial ATA Interface,” page
Table 3-19, page
15. Updated
“Edge Connector for PCI Express Operation,” page
27. Added reference and link to XAPP999 in
Table 3-7, page
to identify FPGA connection of PCIE_PERST. Added PCIE_PERST
Table 3-11, page
www.xilinx.com
Table 4-1, page 89
7. Added link to ML555 website in
as well as
Figure 3-1, page 21
100. Added footnote to
Table 3-26, page
57. Changed signal name for FPGA GCLK input pin AD32
13. Updated
“DDR2 SDRAM SODIMM,” page
33. Added reference and links to Xilinx application
Table 4-4, page
39. Added reference and link to application note
43. Added website link to download Silicon
101.
“USB to UART Bridge,” page
Revision
to recommend Master SelectMAP configuration
40. Corrected FPGA pin assignment for
Table 3-18, page
70. Added footnote to
“Serial Bus Development,” page
to reflect “as built” 30 MHz LVCMOS
Figure 4-5, page
94. Changed oscillator Y2 frequency to
Table 4-7, page 100
Figure 3-8, page
“Kit Contents,” page
53. Changed signal name for
“About the Virtex-5 FPGA
UG201 (v1.4) March 10, 2008
“Reference Designs for
“Platform Flash Image
“Additional
92,
23. Added footnote 6
34. Corrected FPGA
Table 3-37, page
Figure 4-6, page
51. Specify 30 MHz
concerning CCLK
55,
Figure 3-9,
15,
“ML555
15.
86.
98,