HW-V5-PCIE2-UNI-G Xilinx Inc, HW-V5-PCIE2-UNI-G Datasheet - Page 35

• Manufacturer Part Number: HW-V5-PCIE2-UNI-G
• Description: KIT DEV PCIEXPRESS GTX VIRTEX5
• Manufacturer: Xilinx Inc
• Series: Virtex™ -5r
• Type: FPGAr

Specifications of HW-V5-PCIE2-UNI-G

• Contents: Board, CD
• For Use With/related Products: Virtex™-5 FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 3-5: SDRAM Interface Signal Descriptions
Virtex-5 FPGA ML555 Development Kit
UG201 (v1.4) March 10, 2008
SODIMM
Front
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
11
1
3
5
7
9
R
DDR2_VREF
DQS0_B
DQS1_B
DQS2_B
Signal
DQS0
DQS1
DQ10
DQ11
DQ16
DQ17
GND
GND
GND
GND
GND
GND
GND
GND
GND
DQ0
DQ1
DQ2
DQ3
DQ8
DQ9
the DQ and DQS ports on the SODIMM side of the interface. The Xilinx Digitally
Controlled Impedance (DCI) standard SSTL18_I_DCI can be utilized to terminate
unidirectional address and control signals transmitted by the FPGA. External 50 Ω
reference resistors are provided to VRN and VRP for the memory interface banks of the
XC5VLX50T FPGA. See the Virtex-5 FPGA User Guide for additional information on DCI.
For assistance designing a DDR2 interface, refer to the Xilinx Memory Corner website at:
www.xilinx.com/products/design_resources/mem_corner/.
For application assistance specifically for Virtex-5 FPGA DDR2 memory controllers, refer
to XAPP858
Guide
using Virtex-5 FPGAs.
FPGA Pin
[Ref 10]
AA31
AA30
AB31
AC30
AB30
AC29
AF31
W24
W26
W31
V24
V28
V27
Y26
Y31
[Ref 8]
contains detailed technical information for designing memory controllers
NC
(1)
NC
NC
NC
NC
NC
NC
NC
NC
NC
(2)
and XAPP865
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
FPGA
www.xilinx.com
SODIMM
[Ref
Back
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
2
4
6
8
9]. Xilinx Memory Interface Generator (MIG) User
No connect
CK0_B
Signal
DQ12
DQ13
DQ14
DQ15
DQ20
DQ21
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DM0
DM1
DQ4
DQ5
DQ6
DQ7
CK0
FPGA Pin
DDR2 SDRAM SODIMM
AD30
AH10
AF29
AF30
AH9
W25
W27
W29
V25
V30
Y27
V29
Y28
Y29
(1)
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
FPGA
Out
Out
Out
Out
35