HW-V5-PCIE2-UNI-G Xilinx Inc, HW-V5-PCIE2-UNI-G Datasheet - Page 28

• Manufacturer Part Number: HW-V5-PCIE2-UNI-G
• Description: KIT DEV PCIEXPRESS GTX VIRTEX5
• Manufacturer: Xilinx Inc
• Series: Virtex™ -5r
• Type: FPGAr

Specifications of HW-V5-PCIE2-UNI-G

• Contents: Board, CD
• For Use With/related Products: Virtex™-5 FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 3: Hardware Description
Table 3-3: PCI Express Signals, Add-in Card Connector Pin, and FPGA Pins per GTP_DUAL Tile
28
Notes:
1. Signal names are with respect to the add-in card connector slot nomenclature. PETPx and PETNx connect to the endpoint port GTP
2. The PCIE_REFCLK and PERNx differential signals are AC coupled with a 0.1 µF capacitor.
3. Dedicated GTP_DUAL tile assignments are required for 8-lane PCI Express Endpoint interfaces with ES silicon. Production silicon
receiver differential pairs. PERPx and PERNx connect to the endpoint port GTP transmitter differential pairs. Port names at the
connector are with respect to the downstream transmitter and receiver ports. The downstream transmitter/receiver ports connect to
the upstream receiver/transmitter ports, respectively.
removes GTP_DUAL tile assignment restrictions.
PCI Express Signal Name
PCIE_PERST
PERN6
PERN7
PETN6
PETN7
PETP6
PERP6
PETP7
PERP7
See XAPP1022
and debugging PCI Express endpoint applications using the Integrated Endpoint Block for
PCI Express designs available in Virtex-5 LXT FPGAs.
(1)
[Ref 5]
Add-in Card Connector
and XAPP1022
P13 Pin
A43
A44
A47
A48
A11
B41
B42
B45
B46
www.xilinx.com
[Ref 6]
for examples of how to get started designing
FPGA Pin
AE14
AM1
AK2
AN4
AN3
AL1
AL2
AP3
AP2
Virtex-5 FPGA ML555 Development Kit
(2)
UG201 (v1.4) March 10, 2008
GTP_DUAL Tile
Not Applicable
X0Y0
(3)
R