HW-V5-PCIE2-UNI-G Xilinx Inc, HW-V5-PCIE2-UNI-G Datasheet - Page 48

• Manufacturer Part Number: HW-V5-PCIE2-UNI-G
• Description: KIT DEV PCIEXPRESS GTX VIRTEX5
• Manufacturer: Xilinx Inc
• Series: Virtex™ -5r
• Type: FPGAr

Specifications of HW-V5-PCIE2-UNI-G

• Contents: Board, CD
• For Use With/related Products: Virtex™-5 FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 3: Hardware Description
48
Table 3-13: SAMTEC Pin Connections (P33) (Continued)
Notes:
1. These signals are connected to FPGA banks 2 and 18. The FPGA reference voltage for these banks is
2. Bank 2 GPIO clock-capable I/O signals. All others are in FPGA Bank 18.
3. NC = no connect.
4. Bank 18 clock-capable I/O pins.
SAMTEC-QSE-
028-DP P33
2.5V. See ML555 board schematics on the CD-ROM for additional information.
Odd
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
GP1O2_I13_N
GP1O2_I11_N
GP1O2_I01_N
GP1O2_I01_P
GP1O2_I11_P
GP1O2_I09_N
GP1O2_I07_N
GP1O2_I05_N
GP1O2_I03_N
GP1O2_I09_P
GP1O2_I07_P
GP1O2_I05_P
GP1O2_I03_P
No Connect
No Connect
Signal
GND
GND
GND
GND
GND
GND
www.xilinx.com
(1)
(4)
(2)
(4)
(4)
(2)
FPGA
AG23
AF23
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
AH5
AH7
AG5
AG6
AG7
AK7
AK6
AF5
Pin
AJ7
AJ6
Y6
SAMTEC-QSE-
028-DP P33
Even
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
Virtex-5 FPGA ML555 Development Kit
GP1O2_I12_N
GP1O2_I10_N
GP1O2_I00_N
GP1O2_I10_P
GP1O2_I00_P
UG201 (v1.4) March 10, 2008
GP1O2_I08_N
GP1O2_I06_N
GP1O2_I04_N
GP1O2_I02_N
GP1O2_I08_P
GP1O2_I06_P
GP1O2_I04_P
GP1O2_I02_P
No Connect
No Connect
Signal
GND
GND
GND
GND
GND
GND
(1)
(4)
(2)
(4)
(4)
(2)
FPGA
AE22
AE23
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
W11
W10
AF6
V10
Pin
Y11
W7
W9
V7
V8
U8
V9
R