HW-V5-PCIE2-UNI-G Xilinx Inc, HW-V5-PCIE2-UNI-G Datasheet - Page 42

• Manufacturer Part Number: HW-V5-PCIE2-UNI-G
• Description: KIT DEV PCIEXPRESS GTX VIRTEX5
• Manufacturer: Xilinx Inc
• Series: Virtex™ -5r
• Type: FPGAr

Specifications of HW-V5-PCIE2-UNI-G

• Contents: Board, CD
• For Use With/related Products: Virtex™-5 FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 3: Hardware Description
Table 3-10: Ethernet PHY Daughtercard J15 Connection
42
Notes:
1. UG065
2. These signals are connected to FPGA banks 12 and 20. The bank reference voltage, V
3. These clocks are connected to FPGA clock-capable I/O pins.
4. NC = no connect.
on the CD-ROM for additional information.
J15-EVEN
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
2
4
6
8
[Ref 3]
provides additional information on the HW-AFX-BERG-EPHY Daughtercard.
Signal
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
J15-ODD
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
11
1
3
5
7
9
www.xilinx.com
P1_TXC_GTXCLK
P0_TXC_GTXCLK
P1_TXCTL_TXEN
P0_TXCTL_TXEN
P1_TD_TXD1
P1_TD_TXD3
P1_TD_TXD2
P1_TD_TXD0
P0_TD_TXD3
P0_TD_TXD2
P0_TD_TXD1
P0_TD_TXD0
No connect
(1)
P1_MDIO
P0_MDIO
P1_TXD7
P1_TXD6
P1_TXD5
P1_TXD4
P1_TXER
P0_TXD7
P0_TXD6
P0_TXD5
P0_TXD4
RESET_B
P0_TXER
P0_MDC
P1_MDC
P1_COL
P0_COL
P1_INT
P0_INT
Signal
(3)
(3)
CCO
Virtex-5 FPGA ML555 Development Kit
, is 2.5V. See the ML555 board schematics
FPGA Pin
N10
U10
G13
E12
F13
E13
T11
P10
M8
F11
M5
N9
G7
N7
N5
U7
K8
G5
K7
R6
L9
L8
E7
F6
P9
L6
L4
P7
T6
T8
J7
UG201 (v1.4) March 10, 2008
(2)
NC
(4)
FPGA In/Out
In/Out
In/Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
In
In
In
In
R