HW-V5-PCIE2-UNI-G Xilinx Inc, HW-V5-PCIE2-UNI-G Datasheet - Page 94

• Manufacturer Part Number: HW-V5-PCIE2-UNI-G
• Description: KIT DEV PCIEXPRESS GTX VIRTEX5
• Manufacturer: Xilinx Inc
• Series: Virtex™ -5r
• Type: FPGAr

Specifications of HW-V5-PCIE2-UNI-G

• Contents: Board, CD
• For Use With/related Products: Virtex™-5 FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 4: Configuration
Table 4-4: CPLD Pin Listing
94
Number
Pin
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
1
2
3
4
5
6
7
8
9
CPLD_CLK_30MHZ
FLASH_IMAGE0_SELECT
FLASH_IMAGE1_SELECT
GND
FPGA_DONE
FPGA_BUSY_B
VCC2V5
PROG_SW_B
FPGA_TDO
JTAG_TMS
JTAG_TCK
ICS_FSEL2
MAN_AUTO_B
ICS_MR
VCC1V8
ICS_OEA
GND
PB_SW_B
ICS_FSEL1
ICS_FSEL0
CPLD_SPARE1
CPLD_SPARE2
FPGA_CS_B
CPLD_TDO
GND
VCC2V5
INIT_B
PROG_B
WIDE
EDGE_RST_I_B
FORCE
(1)
(1)
Net Name
(1)
Direction
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
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IO/GOE1
Pin Type
IO/GS-R
VCCIO1
IO/GC1
VCCIO2
GND1
GND2
GND3
TMS
VCC
IO10
IO12
IO13
IO14
TDO
IO15
IO16
IO17
TCK
IO11
TDI
IO1
IO2
IO3
IO4
IO5
IO6
IO7
IO8
IO9
I
30 MHz Global Clock Input
Revision Select Pin 0 from Header P3
Revision Select Pin 1 from Header P3
Ground
DONE pin from FPGA
DOUT Busy pin from FPGA
2.5V I/O Power
Input from Pushbutton SW6
JTAG TDI from FPGA
JTAG TMS
JTAG TCK
CPLD output to ICS874003-02 FSEL2 input
Manual/Auto Select pin from Header P3
CPLD output to ICS874003-02 master reset input
1.8V Power
CPLD output to ICS874003-02 output enable port
A input
Ground
CPLD input from Pushbutton SW7. Pin 18 is CPLD
input only.
CPLD output to ICS874003-02 FSEL1 input
CPLD output to ICS874003-02 FSEL0 input
Spare I/O connected to FPGA pin B12
Spare I/O connected to FPGA pin A13
Chip Select from FPGA
JTAG TDO to Flash
Ground
2.5V I/O Power
Output connected to INIT_B pin of FPGA
Output connected to PROG_B pin of FPGA
Output connected to Pin F12 of FPGA
Input connected from Pin A15 of Edge PCI
Output connected to Pin F13 of FPGA
Virtex-5 FPGA ML555 Development Kit
Description
UG201 (v1.4) March 10, 2008
R