HW-V5-PCIE2-UNI-G Xilinx Inc, HW-V5-PCIE2-UNI-G Datasheet - Page 41

• Manufacturer Part Number: HW-V5-PCIE2-UNI-G
• Description: KIT DEV PCIEXPRESS GTX VIRTEX5
• Manufacturer: Xilinx Inc
• Series: Virtex™ -5r
• Type: FPGAr

Specifications of HW-V5-PCIE2-UNI-G

• Contents: Board, CD
• For Use With/related Products: Virtex™-5 FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SMA Connectors
Ethernet PHY Daughtercard Support
Virtex-5 FPGA ML555 Development Kit
UG201 (v1.4) March 10, 2008
R
The ML555 board has a set of SMA connectors to facilitate routing one set of GTP
transceiver signals off the card to an external device. Another set of SMA connectors is also
provided to input a clock to the GTP MGTREFCLK inputs. There are a number of Xilinx
evaluation boards that convert an SMA interface to SATA, RJ45, or SFP, for example.
GTP_DUAL tile X0Y5 is connected to the SMA connectors.
Table 3-9
connectors interface to GTP_DUAL tile X0Y5.
Table 3-9: SMA Connector
The ML555 board provides a Xilinx Generic Interface (XGI) connector system wired to
support attachment of the Xilinx Ethernet PHY Daughtercard, part number HW-AFX-
BERG-EPHY. The EPHY daughtercard is not included with the development kit but can be
purchased separately. The XC5VLX50T FPGA has up to four embedded tri-mode Ethernet
MAC blocks that provide the data link layer interface to the external PHY. The Xilinx
library of soft Ethernet LogiCORE products can also provide Ethernet connectivity
solutions.
The PHY daughtercard contains two Marvell Alaska Gigabit Ethernet over copper
transceivers, part number 88E1111. The PHY devices perform all physical layer functions,
operate at 10/100/1000 Mb/s and support the embedded tri-mode Ethernet MAC within
the Virtex-5 XC5VLX50T FPGA.
The PHY supports GMII, MII, SGMII, and RGMII Ethernet physical interfaces.
The ML555 board contains a 125 MHz oscillator used for the embedded tri-mode EMAC
reference clock.
The ML555 development kit contains two plastic standoffs used with the PHY daughter
card for mechanical support. Refer to UG065
and PHY daughtercard, because the configuration headers on both boards must be set up
properly before power is applied.
Table 3-10
respectively.
Notes:
1. DC blocking capacitors should be installed between the test equipment and the SMA connector when
clocking the GTP transceiver with an external clock source.
SMA Reference
Designator
J12
J13
lists the signal names and pin assignments for the SMA connectors. SMA
J6
J7
J8
J9
and
(1)
(1)
Table 3-11
SMA_GTPCLK_P3_N
SMA_GTPCLK_P4_P
list the signal and pin assignments for the J15 and J16 connectors,
www.xilinx.com
Signal Name
SMA_TXN
SMA_RXN
SMA_TXP
SMA_RXP
[Ref 3]
before powering up the ML555 board
FPGA Pin
D2
D1
C1
E2
P4
P3
SMA Connectors
FPGA I/O
Out
Out
In
In
In
In
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