HW-V5-PCIE2-UNI-G Xilinx Inc, HW-V5-PCIE2-UNI-G Datasheet - Page 98

• Manufacturer Part Number: HW-V5-PCIE2-UNI-G
• Description: KIT DEV PCIEXPRESS GTX VIRTEX5
• Manufacturer: Xilinx Inc
• Series: Virtex™ -5r
• Type: FPGAr

Specifications of HW-V5-PCIE2-UNI-G

• Contents: Board, CD
• For Use With/related Products: Virtex™-5 FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 4: Configuration
98
From P2
Notes:
1. FORCE, WIDE, PCIW_EN, and RTR are FPGA general-purpose I/Os.
To P2
CLKOUT
CLKIN
Generic Dynamic Reconfiguration
Platform Flash
XCF32PF
Platform Flash
U1
Table 4-6: Bitstream Selection Setting for Header P3
It is possible to dynamically reconfigure the entire FPGA after power-up. With this
method, the CPLD loads a predetermined, default bitstream from the Platform Flash upon
power-up. After initial configuration, the FPGA can signal to the CPLD that it wants to be
reconfigured with a different bitstream, using the CPLD_SPARE[1:10] pins. The FPGA
XCF32PF
Figure 4-6: CPLD Configuration for Static Configuration
U15
OE/RESET
REV_SEL0
REV_SEL1
CE1 (U15)
CE (U1)
1
3
5
D[0:7]
BUSY
P3
Bitstream Revision
CF
2
4
6
0 (U15)
1 (U15)
0 (U1)
1 (U1)
www.xilinx.com
43
44
39
40
12
36
42
41
8
2
XC2C32
CPLD
U6
3
8
13
1
31
29
33
32
34
23
28
27
30 MHz
5
6
CPLD
CLK
Virtex-5 FPGA ML555 Development Kit
10
Jumper Settings for P3
DIP SW
From/To P2
1-2, 3-4, and 5-6
SW5
3-4 and 5-6
1-2 and 5-6
UG201 (v1.4) March 10, 2008
D[7:0]
FORCE
WIDE
PCIW_EN
RTR
DONE
DOUT_BUSY
RDWR_B
CS_B
PROG_B
INIT_B
CPLD_SPARE[1:10]
CCLK
5-6
(1)
(1)
XC5VLX50T
(1)
(1)
FPGA
U10
M0 M1 M2
UG201_c4_06_022608
R