HW-V5-PCIE2-UNI-G Xilinx Inc, HW-V5-PCIE2-UNI-G Datasheet - Page 8

• Manufacturer Part Number: HW-V5-PCIE2-UNI-G
• Description: KIT DEV PCIEXPRESS GTX VIRTEX5
• Manufacturer: Xilinx Inc
• Series: Virtex™ -5r
• Type: FPGAr

Specifications of HW-V5-PCIE2-UNI-G

• Contents: Board, CD
• For Use With/related Products: Virtex™-5 FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Preface: About This Guide
8
•
•
•
•
•
•
•
•
The following documents provide supplemental material useful to this user guide:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. UG086, Xilinx Memory Interface Generator (MIG) User Guide
11. XAPP870, Serial ATA Physical Link Initialization with the GTP Transceiver of Virtex-5 LXT
Virtex-5 FPGA RocketIO GTP Transceiver User Guide
This user guide describes the RocketIO™ GTP transceivers available in the Virtex-5
LXT and SXT platform devices.
Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC User Guide
This user guide describes the dedicated Tri-Mode Ethernet Media Access Controller
available in the Virtex-5 LXT and SXT platform devices.
Virtex-5 Integrated Endpoint Block User Guide for PCI Express Designs
This user guide describes the integrated Endpoint blocks in the Virtex-5 LXT and SXT
platform devices for PCI Express
Virtex-5 FPGA XtremeDSP Design Considerations
This guide describes the XtremeDSP™ slice and includes reference designs for using
the DSP48E.
Virtex-5 FPGA Configuration Guide
This all-encompassing configuration guide includes chapters on configuration
interfaces (serial and SelectMAP), bitstream encryption, Boundary-Scan and JTAG
configuration, reconfiguration techniques, and readback through the SelectMAP and
JTAG interfaces.
Virtex-5 FPGA System Monitor User Guide
The System Monitor functionality available in all the Virtex-5 devices is outlined in
this guide.
Virtex-5 FPGA Packaging Specifications
This specification includes the tables for device/package combinations and maximum
I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and
thermal specifications.
Virtex-5 PCB Designer’s Guide
This guide provides information on PCB design for Virtex-5 devices, with a focus on
strategies for making design decisions at the PCB and interface level.
DS090, CoolRunner-II CPLD Family
DS123, Platform Flash In-System Programmable Configuration PROMs
UG065, PHY Daughter Card User Guide
XAPP938, Dynamic Bus Mode Reconfiguration of PCI-X and PCI Designs
XAPP1022, Using the Memory Endpoint Test Driver (MET) with the Programmed Input/Output
Example Design for PCI Express Endpoint Cores
XAPP1002, Using ChipScope Pro to Debug Endpoint Block Plus Wrapper, Endpoint, and Endpoint
PIPE Designs for PCI Express
XAPP999, Reference System: PLBv46 PCI Using the ML555 Embedded Development Platform
XAPP858, High-Performance DDR2 SDRAM Interface in Virtex-5 Devices
XAPP865, Hardware Accelerator for RAID6 Parity Generation / Data Recovery Controller with
ECC and MIG DDR2 Controller
FPGAs
www.xilinx.com
®
designs.
Virtex-5 FPGA ML555 Development Kit
UG201 (v1.4) March 10, 2008
R