HW-V5-PCIE2-UNI-G Xilinx Inc, HW-V5-PCIE2-UNI-G Datasheet - Page 92

• Manufacturer Part Number: HW-V5-PCIE2-UNI-G
• Description: KIT DEV PCIEXPRESS GTX VIRTEX5
• Manufacturer: Xilinx Inc
• Series: Virtex™ -5r
• Type: FPGAr

Specifications of HW-V5-PCIE2-UNI-G

• Contents: Board, CD
• For Use With/related Products: Virtex™-5 FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 4: Configuration
Table 4-3: FPGA Configuration Pin Listing
92
Number
From P2
Notes:
1. FORCE, WIDE, PCIW_EN, and RTR are FPGA general-purpose I/Os.
AD21
AC22
AD22
M22
N15
N23
N22
N14
Pin
To P2
FPGA_CCLK
FPGA_RDWR_B
FPGA_CS_B
MODE0
MODE1
MODE2
PROG_B
INIT_B
Net Name
CLKOUT
CLKIN
Platform Flash
XCF32PF
Figure 4-5: Schematic of Flash/CPLD/FPGA SelectMAP Interface
Platform Flash
U1
XCF32PF
U15
OE/RESET
REV_SEL0
REV_SEL1
CE1 (U15)
1
3
5
CE (U1)
BUSY
P3
D[0:7]
Direction
CF
I/O
2
4
6
I
I
I
I
I
I
I
(1)
36
42
41
43
44
39
40
PROGRAM_B
12 8 2 3 13
RDWR_B
Pin Type
www.xilinx.com
INIT_B
CCLK
CS_B
M0
M1
M2
XC2C32
CPLD
U6
8
CPLD CLK
31
29
33
32
34
23
28
27
1
30 MHz
Configuration Clock Input or Output
Active-Low Read Write
Active-Low Chip Select
Mode Select 0
Mode Select 1
Mode Select 2
Active-Low asynchronous full-chip reset
Active-Low Delay Configuration
5
6
8
1
2
3
4
DIP SW
SW5
From/To P2
Virtex-5 FPGA ML555 Development Kit
D[7:0]
FORCE
WIDE
PCIW_EN
RTR
DONE
DOUT_BUSY
RDWR_B
CS_B
PROG_B
INIT_B
CPLD_SPARE[1:8]
CCLK M0 M1 M2 HSWAPEN
Description
(1)
UG201 (v1.4) March 10, 2008
(1)
(1)
(1)
XC5VLX50T
FPGA
U10
UG201_c4_05_022608
R