HW-V5-PCIE2-UNI-G Xilinx Inc, HW-V5-PCIE2-UNI-G Datasheet - Page 70

• Manufacturer Part Number: HW-V5-PCIE2-UNI-G
• Description: KIT DEV PCIEXPRESS GTX VIRTEX5
• Manufacturer: Xilinx Inc
• Series: Virtex™ -5r
• Type: FPGAr

Specifications of HW-V5-PCIE2-UNI-G

• Contents: Board, CD
• For Use With/related Products: Virtex™-5 FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 3: Hardware Description
Table 3-26: FPGA Clock-Capable I/O Connectivity
70
STROBE
SCLOCK
PCIBUSCLK1
FPGA_CLK_30MHZ
GPIO2_I10_N
GP1O2_I10_P
GPIO2_I11_N
GP1O2_I11_P
GPIO2_I12_N
GP1O2_I12_P
GPIO2_I13_N
GP1O2_I13_P
PLOAD
SDATA
M,N
Signal Name
Clock-Capable I/O Pins Associated with Clock Inputs
T1
Figure 3-13
operation. The parallel mode has priority over serial mode.
Some clock-capable input and output pins of the FPGA are connected to clocking sources
on the ML555 board.
along with their FPGA bank numbers and I/O bank reference voltages.
FPGA Pin FPGA Bank Bank V
T0
Figure 3-13: Serial Configuration Interface Timing
AD32
AG5
AF5
AF6
AE7
L34
W7
W6
V7
Y6
NULL
is a timing diagram showing the serial and parallel programming modes of
STROBE
SCLOCK
N1
PLOAD
SDATA
20 ns min.
M,N
18
11
13
Table 3-26
N0
www.xilinx.com
M8
summarizes these FPGA clock capable inputs and outputs,
100 ns max.
M7
CCO
3.0
3.0
2.5
M6
(Volts)
20 ns min.
User-defined LVDS general-purpose I/O
interface
Regional PCI bus applications
User defined
Virtex-5 FPGA ML555 Development Kit
UG201 (v1.4) March 10, 2008
M2
Function
M1
M0
UG201_c3_12_092706
R