HW-V5-PCIE2-UNI-G Xilinx Inc, HW-V5-PCIE2-UNI-G Datasheet - Page 68

• Manufacturer Part Number: HW-V5-PCIE2-UNI-G
• Description: KIT DEV PCIEXPRESS GTX VIRTEX5
• Manufacturer: Xilinx Inc
• Series: Virtex™ -5r
• Type: FPGAr

Specifications of HW-V5-PCIE2-UNI-G

• Contents: Board, CD
• For Use With/related Products: Virtex™-5 FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 3: Hardware Description
Table 3-25: FPGA Signals for Serial Programming of the Clock Synthesizer Modules
68
PLOAD_1
STROBE_1
SDATA_1
SCLOCK_1
Signal
Serial Mode Operation
The FPGA provides interface signals to program each synthesizer in serial mode.
Table 3-25
clock synthesizer control inputs. A reference design is provided on the CD to demonstrate
serial programming of the clock synthesizer modules from the FPGA.
ICS8442 parallel load input used to parallel-load the multiplier
and divider switch inputs to the device. A pushbutton switch is
provided on the ML555 board to permit the user to load the
settings into the synthesizer. This signal must be a logic “0” level
for serial mode operation.
ICS8442 serial load input used to load serialized multiplier and
divisor constants into the ICS8442. Asserted to perform serial to
parallel loading for user-defined clock synthesis. This signal
should be deasserted during serial data clocking, asserted, and
then deasserted for one clock cycle to complete the serial to
parallel loading of the data into the device.
This signal contains the ICS8442 serial data input. The serial
data is provided in the sequence T1, T0, NULL, N1, N0, M8, M7,
M6, M5, M4, M3, M2, M1, and finally M0. The ICS8442 data
sheet provides a serial loading timing diagram and definitions
for serial data bits.
The ICS8442 serial clock input should only be active during
serial loading of the synthesizer. The clock should be deasserted
at all other times. Data is clocked into the ICS8442 on the rising
edge of the SCLOCK. The ICS8442 data sheet provides a serial
loading timing diagram and definitions for serial data bits.
Logic 0 Position
Example requests ICS1 330 MHz Clock
with M(8:0) = 0x021 and N(1:0) = 00
O
F
F
lists the FPGA outputs and pin assignments that connect directly to the ICS8442
Figure 3-12: Clock Synthesizer Parallel Load Switch Settings
SW10
Logic 1 Position
www.xilinx.com
Description
1: ICS1 - M0
2: ICS1 - M1
3: ICS1 - M2
4: ICS1 - M3
5: ICS1 - M4
6: ICS1 - M5
7: ICS1 - M6
8: ICS1 - N0
Position
Logic 0 Position
Example requests ICS2 150 MHz Clock
with M(8:0) = 0x00C and N(1:0) = 01
Virtex-5 FPGA ML555 Development Kit
O
F
F
SW12
UG201 (v1.4) March 10, 2008
FPGA Pin
Logic 1 Position
AM32
AN33
AN34
AP32
1: ICS2 - M0
2: ICS2 - M1
3: ICS2 - M2
4: ICS2 - M3
5: ICS2 - M4
6: ICS2 - N0
7: ICS2 - N1
8: ICS1 - N1
UG201_c3_11_092706
Position
(1)
Output
Output
Output
Output
In/Out
FPGA
R