HW-V5-PCIE2-UNI-G Xilinx Inc, HW-V5-PCIE2-UNI-G Datasheet - Page 59

• Manufacturer Part Number: HW-V5-PCIE2-UNI-G
• Description: KIT DEV PCIEXPRESS GTX VIRTEX5
• Manufacturer: Xilinx Inc
• Series: Virtex™ -5r
• Type: FPGAr

Specifications of HW-V5-PCIE2-UNI-G

• Contents: Board, CD
• For Use With/related Products: Virtex™-5 FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Virtex-5 FPGA ML555 Development Kit
UG201 (v1.4) March 10, 2008
Parallel Bus Clocking (PCI Operation)
R
PCI Express applications can utilize the system board’s 100 MHz clock input on the GTP
MGTREFCLK clock input or synthesize a 100 MHz clock using the clock synthesizer, a
DCM, and GTP clocking resources. SATA applications must synthesize a 150 MHz clock
using Clock Synthesizer 2. Gigabit Ethernet applications can use either the 125 MHz
oscillator or a synthesized clock. Fibre channel applications must synthesize either a
53.125 MHz or a 106.25 MHz clock. When using the SFP connectors for Fibre channel and
Gigabit Ethernet, the REFCLK for the SFP must be either Fibre channel or Ethernet speed,
and the SMA connectors should be used to route either the Fibre channel or Ethernet
interface to an offboard connector interface.
The SMA connectors are not AC coupled on the ML555 board, so either internal GTP AC
coupling must be enabled or external AC coupling might be required for interfaces to
offboard transceivers to be electrically compatible.
The PCI specification calls for the PCI bus clock, sourced from the motherboard PCI slot, to
have one load on the add-in cards. The LogiCORE solutions for PCI and PCI-X designs,
depending upon bus mode and frequency, require that the PCI bus clock enter the FPGA
on a specific clock pin (refer to
The ML555 board PCI bus clock is implemented as follows:
•
•
•
•
If full electrical compliance is required, the designer has the option to remove one of the
two resistors (R2 or R242). As shipped, the ML555 board has both resistors installed.
The PCI bus clock (signal CLK_FROM_EDGE) enters the board on PCI edge
connector P1 pin B16.
The clock is then routed in a “Y” topology to two parallel resistors, R2 and R242.
The output side of R2 (signal PCIBUSCLK1) is routed to FPGA pin L34 (the regional
clock pin of FPGA).
The output side of R242 (signal PCIBUSCLK2) is routed to FPGA pin J14 (the global
clock pin of FPGA).
www.xilinx.com
Table
1-1).
Clock Generation
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