HW-V5-PCIE2-UNI-G Xilinx Inc, HW-V5-PCIE2-UNI-G Datasheet - Page 72

• Manufacturer Part Number: HW-V5-PCIE2-UNI-G
• Description: KIT DEV PCIEXPRESS GTX VIRTEX5
• Manufacturer: Xilinx Inc
• Series: Virtex™ -5r
• Type: FPGAr

Specifications of HW-V5-PCIE2-UNI-G

• Contents: Board, CD
• For Use With/related Products: Virtex™-5 FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 3: Hardware Description
Table 3-26: FPGA Clock-Capable I/O Connectivity (Continued)
72
DQS2_B
DQS2
DQS1_B
DQS1
DQS0_B
DQS0
DQS5_B
DQS5
DQS4_B
DQS4
DQS3_B
DQS3
DQS7_B
DQS7
DQS6_B
DQS6
SCL
Signal Name
IDELAYCTRL Reference Clock Generation
A 200 MHz reference clock for the IDELAYCTRL block is required if the user application
uses the IOB variable delay elements. The ML555 board provides a dedicated 200 MHz
LVPECL_25 oscillator on the board connected to the global clock inputs as shown in
Table 3-19, page
the FPGA or using one of the clock synthesizers on the board. There are three methods to
generate the reference clock, depending on application usage:
1.
2.
Using a DCM with the DCM CLKFX output:
♦
♦
♦
Using an external signal generator and connecting the signal generator outputs, either
single-ended or differential to the ML555 SMA clock inputs J10 (GCLKP H17) and J11
(GCLKN H18). The frequency generator output is set to the desired frequency. A DCM
is not required for this method of generating the IDELAYCTRL reference clock.
FPGA Pin FPGA Bank Bank V
AA29
AH27
AA30
AC30
AA31
AK27
AK28
AK29
AK11
AD11
AD10
AB30
AB31
AJ26
AJ29
AJ11
AE8
The ML555 30 MHz clock input is used on GCLK pin L19 as the DCM clock input.
The 125 MHz clock input is used through the U2 clock multiplexer GCLK inputs,
G15(P) and G16(N), as the DCM clock input.
The 125 MHz clock input is used through the clock driver GCLK inputs, J20(P)
and J21(N), as the DCM clock input.
57. The IDELAYCTRL reference clock can alternately be generated within
17
21
22
www.xilinx.com
CCO
1.8
1.8
1.8
(Volts)
bytes 2, 1, and 0
bytes 5, 4, and 3
bytes 7 and 6
DDR2 SODIMM serial clock for presence
detection synchronization with the SDA
bidirectional data signal
DDR2 memory data strobes for data
DDR2 memory data strobes for data
DDR2 memory data strobes for data
Virtex-5 FPGA ML555 Development Kit
UG201 (v1.4) March 10, 2008
Function
R