HW-V5-PCIE2-UNI-G Xilinx Inc, HW-V5-PCIE2-UNI-G Datasheet - Page 64

• Manufacturer Part Number: HW-V5-PCIE2-UNI-G
• Description: KIT DEV PCIEXPRESS GTX VIRTEX5
• Manufacturer: Xilinx Inc
• Series: Virtex™ -5r
• Type: FPGAr

Specifications of HW-V5-PCIE2-UNI-G

• Contents: Board, CD
• For Use With/related Products: Virtex™-5 FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 3: Hardware Description
Table 3-22: Clock Synthesizer 1 Frequency Output for Multiplier/Divider Values with a 10 MHz Input Clock
64
Multiplier Input Selection
M8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(hex)
0x00 – 0x18
M[7:0]
1A
1D
2A
2D
1C
2C
1B
1E
1F
2B
2E
2F
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
output clock is not deterministic. Only one output frequency can be generated based upon
the divisor selection.
Frequency Range
Will not LOCK
VCO Lock
(MHz)
250
260
270
280
290
300
310
320
330
340
350
360
370
380
390
400
410
420
430
440
450
460
470
480
490
500
510
520
Frequency
Divisor = 1
N[1:0]=00b
(MHz) with
www.xilinx.com
Output
N/A
250
260
270
280
290
300
310
320
330
340
350
360
370
380
390
400
410
420
430
440
450
460
470
480
490
500
510
520
N[1:0]=01b
Frequency
(MHz) with
Divisor = 2
Output
N/A
125
130
135
140
145
150
155
160
165
170
175
180
185
190
195
200
205
210
215
220
225
230
235
240
245
250
255
260
Virtex-5 FPGA ML555 Development Kit
Frequency (MHz)
with Divisor = 4
N[1:0]=10b
Output
102.5
107.5
122.5
127.5
N/A
112.5
117.5
62.5
67.5
72.5
77.5
82.5
87.5
92.5
97.5
100
105
110
120
125
130
115
UG201 (v1.4) March 10, 2008
65
70
75
80
85
90
95
N[1:0]=11b
Frequency
(MHz) with
Divisor = 8
Output
31.25
33.75
36.25
38.75
41.25
43.75
46.25
48.75
51.25
53.75
56.25
58.75
61.25
63.75
N/A
32.5
37.5
42.5
47.5
52.5
57.5
62.5
35
40
45
50
55
60
65
R