HW-V5-PCIE2-UNI-G Xilinx Inc, HW-V5-PCIE2-UNI-G Datasheet - Page 61

• Manufacturer Part Number: HW-V5-PCIE2-UNI-G
• Description: KIT DEV PCIEXPRESS GTX VIRTEX5
• Manufacturer: Xilinx Inc
• Series: Virtex™ -5r
• Type: FPGAr

Specifications of HW-V5-PCIE2-UNI-G

• Contents: Board, CD
• For Use With/related Products: Virtex™-5 FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Virtex-5 FPGA ML555 Development Kit
UG201 (v1.4) March 10, 2008
Clock Synthesizers
R
The ML555 board contains two clock synthesizer circuits that support a wide range of
frequency synthesis capabilities for end-user applications. One of the clock synthesizers
should be used to generate the clock for the DDR2 SODIMM memory. The second clock
synthesizer can be used to generate the reference clock for the GTP transceivers. Two
Integrated Circuit Systems (ICS) ICS8442 Crystal Oscillator to Differential LVDS
Frequency Synthesizer devices are on the board, each with a different crystal oscillator
reference clock.
The ICS8442 device has the following features:
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The complete data sheet for the ICS8442 device is available online at
http://www.idt.com/products/getDoc.cfm?docID=6914275
The synthesizer multiplies the reference clock input by a selectable multiplier. The VCO
operates (locks) in a range from 250 to 700 MHz. The VCO output is routed through a
programmable divider to generate the desired output frequency. The supported VCO
frequency divisors are 1, 2, 4, or 8. The resultant clock from the divisor block is then routed
to differential output drivers.
The clock synthesizer can be programmed in either parallel or serial mode. Parallel mode
requires the user to set two DIP switches on the ML555 board, and then press and release a
pushbutton switch to load the desired configuration into the ICS8442. Serial configuration is
accomplished using the FPGA to transmit serial data, clock, and controls to the
synthesizer. A reference design to program the ICS clock synthesizers using the FPGA to
ICS8442 serial configuration interface is provided on the reference CD-ROM included with
the ML555 kit.
The output frequency of the synthesizer is M times the input reference clock frequency,
provided that the internal VCO is locked. An eight-position DIP switch selects the
multiplier value, M. M can be any decimal value from 0 to 511. There are values of M
where the VCO will not obtain frequency lock. The relationship between the input clock
(F
The VCO can be divided by an integer value 1, 2, 4, or 8 using the DIP switches as shown
in
The frequency output of the clock synthesizer is given by the equation:
XTAL
Table
Dual differential LVDS outputs
Output frequency range: 31.25 MHz to 700 MHz
Crystal input frequency range: 10 MHz to 25 MHz
VCO operating range: 250 MHz to 700 MHz
Parallel or serial interface for programming multiplier and output dividers
RMS period jitter: 2.7 ps (typical)
Cycle to cycle jitter: 18 ps (typical)
) and the VCO frequency is given by the equation:
F
F
3-21.
VCO
OUT
= F
= F
XTAL
VCO
/N = F
X M
www.xilinx.com
XTAL
X M/N (provided the VCO is locked)
Clock Generation
61