HW-V5-PCIE2-UNI-G Xilinx Inc, HW-V5-PCIE2-UNI-G Datasheet - Page 86

• Manufacturer Part Number: HW-V5-PCIE2-UNI-G
• Description: KIT DEV PCIEXPRESS GTX VIRTEX5
• Manufacturer: Xilinx Inc
• Series: Virtex™ -5r
• Type: FPGAr

Specifications of HW-V5-PCIE2-UNI-G

• Contents: Board, CD
• For Use With/related Products: Virtex™-5 FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 3: Hardware Description
XCF32PFS48C Platform Flash U1 and U15
Table 3-37: Platform Flash Image Selection
86
Notes:
1. See XAPP1022
(P3-5 to P3-6)
design function in a PC using a memory endpoint test driver.
MAN_AUTO
SHUNT ON
SHUNT ON
SHUNT ON
SHUNT ON
[Ref
5]. This application note demonstrates how to generate an Endpoint Block Plus PIO example design and test the
FLASH_IMAGE1_SEL
(P3-3 to P3-4)
Figure 4-5, page 92
the XC5VLX50T FPGA U10 and the XC2C32 CPLD U6.
The XCF32PFS48C V
The Platform Flash holds up to four configuration images for the XC5VLX50T FPGA, two
images in each device. As shown in
applying shorting blocks to header P3. When generating design images for the ML555
board, the BITGEN “compress” option is not required to store four design images in the
Platform Flash device.
image files depending upon how shunts are installed on header P3.
In concert with the XC2C32 CPLD, the XCF32PFS48C supports static and dynamic
reconfiguration of the FPGA.
concerning the ML555 board configuration.
SHUNT OFF
SHUNT OFF
SHUNT ON
SHUNT ON
FLASH_IMAGE0_SEL
and
CCO
Table 3-37
(P3-1 to P3-2)
SHUNT OFF
Table 4-5, page 95
SHUNT OFF
SHUNT ON
SHUNT ON
is 2.5V.
www.xilinx.com
Chapter 4, “Configuration,”
shows how to select each one of the four configuration
Figure
summarize the Platform Flash connections to
4-5, the configuration image is selected by
Configure FPGA with Platform Flash U1 Image
0 (4-lane Virtex-5 LogiCORE Endpoint block for
PCI Express memory completer design)
Configure FPGA with Platform Flash U1 Image
1 (8-lane Virtex-5 FPGA LogiCORE Endpoint
block for PCI Express memory completer
design)
Configure FPGA with Platform Flash U15 Image
0 (32-bit, 33 MHz memory reference design for
PCI operation)
Configure FPGA with Platform Flash U15 Image
1 (64-bit, 133 MHz memory reference design for
PCI-X operation)
FPGA Configuration Image Selected
Virtex-5 FPGA ML555 Development Kit
provides more details
UG201 (v1.4) March 10, 2008
(1)
R