HW-V5-PCIE2-UNI-G Xilinx Inc, HW-V5-PCIE2-UNI-G Datasheet - Page 96

• Manufacturer Part Number: HW-V5-PCIE2-UNI-G
• Description: KIT DEV PCIEXPRESS GTX VIRTEX5
• Manufacturer: Xilinx Inc
• Series: Virtex™ -5r
• Type: FPGAr

Specifications of HW-V5-PCIE2-UNI-G

• Contents: Board, CD
• For Use With/related Products: Virtex™-5 FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 4: Configuration
Table 4-5: Pin Listing for Platform Flash (Continued)
96
Number
Pin
H5
D5
A5
A6
H4
A3
G3
G4
H3
A1
A2
H1
G6
H2
D6
G5
A4
E5
C5
B5
E6
E2
B6
B1
E1
B2
C6
C3
C4
F1
F5
F6
FLASH_D1
FLASH_D2
FLASH_D3
FLASH_D4
FLASH_D5
FLASH_D6
FLASH_D7
FLASH_EN_EXT_SEL_B
FLASH_OE_RESET_B
FLASH_REV_SEL0
FLASH_REV_SEL1
JTAG_TCK
JTAG_TDO
JTAG_TMS
GND
GND
GND
GND
GND
GND
GND
VCC1V8
VCC1V8
VCC1V8
VCC1V8
VCC2V5
VCC2V5
VCC2V5
VCC2V5
Unused
Unused
Unused
Net Name
Direction
I/O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
EN_EXT_SEL
OE/RESET
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REV_SEL0
REV_SEL1
VCCINT1
VCCINT2
VCCINT3
Pin Type
VCCJ
VCCO3
VCCO1
VCCO2
VCCO4
GND1
GND2
GND3
GND4
GND5
GND6
GND7
DNC1
DNC2
DNC3
TDO
TMS
TCK
D1
D2
D3
D4
D5
D6
D7
(1)
SelectMAP data bit 1 connected to FPGA
SelectMAP data bit 2 connected to FPGA
SelectMAP data bit 3 connected to FPGA
SelectMAP data bit 4 connected to FPGA
SelectMAP data bit 5 connected to FPGA
SelectMAP data bit 6 connected to FPGA
SelectMAP data bit 7 connected to FPGA
Enable External Selection input – tied Low
Output Enable / Active-Low Reset
Revision Select 0 input connected to CPLD Pin 39
Revision Select 1 input connected to CPLD Pin 40
JTAG TCK
JTAG TDO connected to Header P5
JTAG TMS
Ground
Ground
Ground
Ground
Ground
Ground
Ground
1.8V Power
1.8V Power
1.8V Power
1.8V Power
2.5V I/O Power
2.5V I/O Power
2.5V I/O Power
2.5V I/O Power
Do Not Connect
Do Not Connect
Do Not Connect
Virtex-5 FPGA ML555 Development Kit
Description
UG201 (v1.4) March 10, 2008
R