HW-V5-PCIE2-UNI-G Xilinx Inc, HW-V5-PCIE2-UNI-G Datasheet - Page 85

• Manufacturer Part Number: HW-V5-PCIE2-UNI-G
• Description: KIT DEV PCIEXPRESS GTX VIRTEX5
• Manufacturer: Xilinx Inc
• Series: Virtex™ -5r
• Type: FPGAr

Specifications of HW-V5-PCIE2-UNI-G

• Contents: Board, CD
• For Use With/related Products: Virtex™-5 FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XC2C32 CoolRunner-II CPLD U6
Virtex-5 FPGA ML555 Development Kit
UG201 (v1.4) March 10, 2008
ML555 Board Physical Dimensions
R
The ML555 board cannot margin any of the oncard power supplies. Other Xilinx boards
have power supply monitoring and margining capabilities for application-specific
functions, such as memory interfaces and LVDS interfaces. Characterization boards are
available for GTP transceiver characterization.
The physical height of the ML555 board prevents the system unit covers from being used.
The ML555 board should only be used in a development environment. The ML555 board is
4.7 inches high by 10.5 inches long.
This CPLD supports static or dynamic reconfiguration of the FPGA design image. A
default design image for the CPLD is provided with the ML555 board to support static
reconfiguration. To select one of four designs, the user configures the P3 configuration
image select header and then either powers up the board, or depresses and releases the
PROG switch while the board is in a system unit. The design image might require the
board to be plugged into either a parallel PCI bus system board slot or a serial PCI Express
system board slot.
Figure 4-5, page 92
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•
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All XC2C32 I/O are 2.5V, and the XC2C32 V
includes more details concerning the ML555 board configuration.
U1 and U15: XCF32PFSG48C Platform Flash configuration devices
U10: XC5VLX50T FPGA Bank 20
U10: XC5VLX50T FPGA Bank 0 Configuration Interface
P3: Configuration Image select header
SW6 (PROG), SW7: General-purpose pushbutton switches
and
Table 4-4, page 94
www.xilinx.com
summarize the CPLD connections to:
CCINT
is 1.8V.
XC2C32 CoolRunner-II CPLD U6
Chapter 4, “Configuration,”
85