HW-V5-PCIE2-UNI-G Xilinx Inc, HW-V5-PCIE2-UNI-G Datasheet - Page 93

• Manufacturer Part Number: HW-V5-PCIE2-UNI-G
• Description: KIT DEV PCIEXPRESS GTX VIRTEX5
• Manufacturer: Xilinx Inc
• Series: Virtex™ -5r
• Type: FPGAr

Specifications of HW-V5-PCIE2-UNI-G

• Contents: Board, CD
• For Use With/related Products: Virtex™-5 FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 4-3: FPGA Configuration Pin Listing
Virtex-5 FPGA ML555 Development Kit
UG201 (v1.4) March 10, 2008
Notes:
1. Configuration signals are connected to FPGA bank 0. The reference voltage, V
2. These signals are connected to FPGA bank 20. The FPGA reference voltage, V
3. The Net Names and Directions for pins L11, L10, C13, and B13 were chosen to support a specific PCI/PCI-X design as described in
4. Use LVCMOS_25 I/O standard for general-purpose I/O connected to the CPLD.
5. The Platform Flash data bus is connected to FPGA Bank 2. The FPGA reference voltage, V
Number
AD19,
AD15
AD20
AE19
AE17
AF16
AE21
AE16
AF15
M15
A13
C13
schematics on the CD-ROM for additional information.
schematics on the CD-ROM for additional information.
“CPLD Programming Examples.”
data bit 0 is also connected to FPGA bank 0 to support the Serial SelectMAP configuration.
Pin
P15
L11
L10
B13
B12
H9
FPGA_DONE
FPGA_BUSY_B
FLASH_D0
FLASH_D1
FLASH_D2
FLASH_D3
FLASH_D4
FLASH_D5
FLASH_D6
FLASH_D7
FORCE
WIDE
PCIW_EN
RTR
CPLD_SPARE1
CPLD_SPARE2
CPLD_SPARE3
R
(2,3,4)
Net Name
(2,3,4)
(2,3,4)
(2,3,4)
(5)
(5)
(5)
(5)
(5)
(5)
(5)
(5)
(2,4)
(2,4)
(2,4)
The user can use these pins as spare, bidirectional pins.
Direction
I/O
I/O
I/O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
(1)
DOUT_BUSY
(Continued)
Pin Type
www.xilinx.com
DONE
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Active-High signal indicating configuration is
complete
Active-Low Busy signal
SelectMAP data bit 0 connected to Platform Flash
device
SelectMAP data bit 1 connected to Platform Flash
device
SelectMAP data bit 2 connected to Platform Flash
device
SelectMAP data bit 3 connected to Platform Flash
device
SelectMAP data bit 4 connected to Platform Flash
device
SelectMAP data bit 5 connected to Platform Flash
device
SelectMAP data bit 6 connected to Platform Flash
device
SelectMAP data bit 7 connected to Platform Flash
device
Input connected from Pin 31 of Platform Flash
device
Input connected from Pin 29 of CPLD
Output connected to Pin 33 of CPLD
Output connected to Pin 32 of CPLD
Spare I/O connected to CPLD pin 21
Spare I/O connected to CPLD pin 22
Spare I/O connected to CPLD pin 36
CCO
CCO
, for this bank is 2.5V. See the ML555 board
, for this bank is 2.5V. See the ML555 board
CCO
, for this bank is 2.5V. Platform Flash
Description
SelectMAP Interface
93