HW-V5-PCIE2-UNI-G Xilinx Inc, HW-V5-PCIE2-UNI-G Datasheet - Page 30

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HW-V5-PCIE2-UNI-G

Manufacturer Part Number
HW-V5-PCIE2-UNI-G
Description
KIT DEV PCIEXPRESS GTX VIRTEX5
Manufacturer
Xilinx Inc
Series
Virtex™ -5r
Type
FPGAr

Specifications of HW-V5-PCIE2-UNI-G

Contents
Board, CD
For Use With/related Products
Virtex™-5 FPGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HW-V5-PCIE2-UNI-G
Manufacturer:
XILINX
0
Chapter 3: Hardware Description
Table 3-4: P1 PCI Edge Connector Pinout
30
32-Bit Connector
P1 A
Side
A10
A11
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A1
A2
A3
A4
A5
A6
A7
A8
A9
unused
VCC12
unused
EDGE_JTAG
VCC5
EDGE_INTA_B
EDGE_INTC_B
VCC5
unused
VCC3V3
unused
3.3V KEY
3.3V KEY
AUXV
EDGE_RST_B
VCC3V3
EDGE_GNT_B
GND
EDGE_PME_B
EDGE_AD30
VCC3V3
EDGE_AD28
EDGE_AD26
GND
EDGE_AD24
EDGE_IDSEL
VCC3V3
EDGE_AD22
EDGE_AD20
GND
EDGE_AD18
Signal
Table 3-4
side A, and the non-component side or the back of the PCB is side B.
FPGA Pin
shows the edge connector (P1) pin assignment. The component side of the PCB is
H30
N29
N30
L30
L31
P30
R29
P29
R31
T30
T29
J31
J30
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
(1)
(2)
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
FPGA
Out
Out
Out
I/O
www.xilinx.com
In
In
In
P1 B
Side
B10
B11
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B1
B2
B3
B4
B5
B6
B7
B8
B9
VCC_MINUS12
unused
GND
EDGE_JTAG
VCC5
VCC5
EDGE_INTB_B
EDGE_INTD_B
GND
unused
unused
3.3V KEY
3.3V KEY
unused
GND
CLK_FROM_EDGE
GND
EDGE_REQ_B
VCC3V3
EDGE_AD31
EDGE_AD29
GND
EDGE_AD27
EDGE_AD25
VCC3V3
EDGE_CBE3
EDGE_AD23
GND
EDGE_AD21
EDGE_AD19
VCC3V3
Signal
Virtex-5 FPGA ML555 Development Kit
(3)
UG201 (v1.4) March 10, 2008
FPGA Pin
L34, J14
M30
M31
G31
K29
K31
R28
U30
P31
F33
T31
T28
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
(1)
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
FPGA
Out
Out
Out
I/O
In
R

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