HW-V5-PCIE2-UNI-G Xilinx Inc, HW-V5-PCIE2-UNI-G Datasheet - Page 91

• Manufacturer Part Number: HW-V5-PCIE2-UNI-G
• Description: KIT DEV PCIEXPRESS GTX VIRTEX5
• Manufacturer: Xilinx Inc
• Series: Virtex™ -5r
• Type: FPGAr

Specifications of HW-V5-PCIE2-UNI-G

• Contents: Board, CD
• For Use With/related Products: Virtex™-5 FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SelectMAP Interface
Virtex-5 FPGA ML555 Development Kit
UG201 (v1.4) March 10, 2008
R
Table 4-2: P5 JTAG Header Signal Descriptions and Pin Assignments
The SelectMAP interface is connected to the Platform Flash devices indirectly through the
CPLD. For the SelectMAP interface to operate correctly, the CPLD needs to be
programmed (via JTAG) such that the correct connections are made between the FPGA
and the Flash. The CPLD on the ML555 board has a default image programmed into the
device to permit selection of up to four static design images in the two Platform Flash
configuration devices. The source HDL code and CPLD constraint file are located on the
CD-ROM provided with the ML555 kit.
Figure 4-5
Table 4-3
respectively. The two Platform Flash devices are connected in parallel, with the exception
of the chip-enable inputs. The CPLD has one chip-enable output for each Platform Flash
device.
Notes:
1. This JTAG connectivity assumes that all four devices are in the JTAG configuration chain.
2. The JTAG_TDO connection is made to the second Platform Flash device, U15. The JTAG_TMS and
Signal Name
JTAG_TMS
JTAG_TCK
JTAG_TDO
JTAG_TDI
JTAG_TCK signals are connected to both U1 and U15 Platform Flash devices.
through
is a general schematic for the Flash/CPLD/FPGA SelectMAP Interface.
JTAG TMS to
FPGA/CPLD/Flash
JTAG TCK to
FPGA/CPLD/Flash
JTAG TDO from Flash
JTAG TDI to FPGA TDI
Table 4-5
Description
www.xilinx.com
list the pinouts for the FPGA, CPLD, and Platform Flash,
Number
P5 Pin
10
4
6
8
FPGA Pin
Number
AC14
AC15
AB15
N/A
CPLD Pin
Number
N/A
N/A
SelectMAP Interface
10
11
Flash Pin
Number
N/A
E6
H3
E2
(2)
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