HW-V5-PCIE2-UNI-G Xilinx Inc, HW-V5-PCIE2-UNI-G Datasheet - Page 53

• Manufacturer Part Number: HW-V5-PCIE2-UNI-G
• Description: KIT DEV PCIEXPRESS GTX VIRTEX5
• Manufacturer: Xilinx Inc
• Series: Virtex™ -5r
• Type: FPGAr

Specifications of HW-V5-PCIE2-UNI-G

• Contents: Board, CD
• For Use With/related Products: Virtex™-5 FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 3-18: ML555 Board Clock Sources
Virtex-5 FPGA ML555 Development Kit
UG201 (v1.4) March 10, 2008
Clock Designator
Y1
Y2
Y3
P1 pin B16
U18 Clock
Synthesizer 1
U19 Clock
Synthesizer 2
J10
J11
J12
J13
PCIE_REFCLKP
(5)
(5)
R
(3)
(4)
Differential only
(system board
Differential
Single-Ended
Differential
Single-Ended
Differential
Differential
Single-Ended
Differential/
Differential
Differential
Differential
Output
input)
Table 3-18
regional clock input and a global clock input of the FPGA as shown in
differential 100 MHz reference clock input for PCI Express designs (PCIE_REFCLK{P/N})
is described in
(PCI Express Operation),” page
inputs as well as global clock inputs.
(1)
(1)
(1)
(1)
lists the destination pins of these clock sources. The PCI bus clock goes to a
LVCMOS
PCI 3.3V
LVPECL
LVDS
LVDS
LVDS
LVDS
Input
Input
Input
Input
Type
SMA
SMA
SMA
SMA
“Serial Bus Clocking with Optional ICS874003-02 Clock Jitter Attenuator
(6)
User-Specified
User-Specified
User Specified GTP_DUAL tile X0Y3 MGTREFCLK_P pin P4
User Specified GTP_DUAL tile X0Y3 MGTREFCLK_N pin P3
31.25 MHz to
31.25 MHz to
Frequency
700 MHz
700 MHz
33 MHz to
Spectrum
GCLK_N
125 MHz
200 MHz
133 MHz
100 MHz
GCLK_P
www.xilinx.com
30 MHz
Spread
60. The two clock synthesizer outputs go to GTP REFCLK
(2)
(2)
Refer to
Clock Buffer U9 input pin 1 (P) then to FPGA U10
Bank 3 L19 (P). See
clock distribution.
FPGA U10 Bank 3 K17 (P) and L18 (N)
FPGA U10 Bank 3 J14 Global Clock (P)
FPGA U10 Bank 3 Regional Clock input pin L34 (P)
Refer to
Refer to
SMA_GCLKP FPGA U10 Bank 3 Global Clock input
pin H17 (P)
(Must not be connected to a single-ended clock)
SMA_GCLKN FPGA U10 Bank 3 Global Clock
differential input pin H18 (N)
FPGA U10 GTP_DUAL tile X0Y2 MGTREFCLK_P
pin Y4 and FPGA U10 global clock input pin J16 as
PCIE_GCLK_P
Figure
Figure
Figure
3-8.
3-8.
3-8.
Destination Pin
Figure 4-8, page 100
Table
Clock Generation
3-18. The
for 30 MHz
53