HW-V5-PCIE2-UNI-G Xilinx Inc, HW-V5-PCIE2-UNI-G Datasheet - Page 38

• Manufacturer Part Number: HW-V5-PCIE2-UNI-G
• Description: KIT DEV PCIEXPRESS GTX VIRTEX5
• Manufacturer: Xilinx Inc
• Series: Virtex™ -5r
• Type: FPGAr

Specifications of HW-V5-PCIE2-UNI-G

• Contents: Board, CD
• For Use With/related Products: Virtex™-5 FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 3: Hardware Description
Table 3-5: SDRAM Interface Signal Descriptions (Continued)
38
Notes:
1. DDR2 memory interface signals are connected to FPGA banks 4, 17, 21, and 22. The FPGA reference voltage, V
2. NC = no connect.
3. Pin 115 (S1_B) is a no connect because the ML555 board does not support dual-rank SODIMMs.
SODIMM
Front
is 1.8V. See the ML555 board schematics on the CD-ROM for further information.
183
185
187
189
191
193
195
197
199
DDR2_VCC1V8
Signal
DQ58
DQ59
GND
GND
GND
DM7
SDA
SCL
Power consumption for the DDR2 memory interface is dependent upon the density and
speed of DDR2 memory installed in the SODIMM socket.
1.8V current consumption requirements by density and transfer rate for Micron
Semiconductor SODIMMs supported by the ML555 board. Memory data sheet
specifications should be consulted to determine specific power requirements for the
SODIMM memory devices. Higher densities and higher performance SODIMMs are
supported, however, the user must calculate total application power and stay within the
PCI and/or PCI Express add-in card specifications.
Table 3-6: DDR2 SODIMM Current Consumption versus Data Transfer Rate
Current consumption can be higher than shown in
interleaved in the DDR2 memory. Interleaving is accomplished by using the BA[2:0] bank
address as the least-significant column address bits to the DDR2 memory. This increases
power dissipation rather than memory performance, and should be avoided for PCI
Express and PCI bus applications where add-in card power is limited by specification to
25W.
Memory Density
FPGA Pin
128 MB
256 MB
512 MB
AM12
AM11
AD9
AE8
AJ9
(1)
NC
NC
NC
NC
In/Out
In/Out
In/Out
In/Out
FPGA
Out
Out
www.xilinx.com
400 MT/s
480 mA
620 mA
720 mA
SODIMM
Back
184
186
188
190
192
194
196
198
200
GND(SA0)
GND(SA1)
DQS7_B
Signal
DQS7
DQ62
DQ63
GND
GND
GND
Table 3-6
533 MT/s
720 mA
780 mA
780 mA
Virtex-5 FPGA ML555 Development Kit
Table 3-6
if the four memory banks are
UG201 (v1.4) March 10, 2008
FPGA Pin
AK11
AJ11
AK9
AF9
shows approximate
CCO
(1)
NC
NC
NC
NC
NC
667 MT/s
1100 mA
860 mA
940 mA
, for these banks
In/Out
In/Out
In/Out
In/Out
In/Out
FPGA
R