HW-V5-PCIE2-UNI-G Xilinx Inc, HW-V5-PCIE2-UNI-G Datasheet - Page 90

• Manufacturer Part Number: HW-V5-PCIE2-UNI-G
• Description: KIT DEV PCIEXPRESS GTX VIRTEX5
• Manufacturer: Xilinx Inc
• Series: Virtex™ -5r
• Type: FPGAr

Specifications of HW-V5-PCIE2-UNI-G

• Contents: Board, CD
• For Use With/related Products: Virtex™-5 FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 4: Configuration
JTAG Port
90
Connector
JTAG
P5
TDI
TMS
TCK
connector/header P38 is used to enable or bypass the Platform Flash device U1, and
connector/header P20 is used to enable or bypass the second Platform Flash device U15.
To enable the CPLD for JTAG configuration, the shunts on P39 are connected from pin 1 to
pin 2, and a second shunt connects pin 3 to pin 4. To bypass the CPLD, a single shunt is
installed on P39, connected from pin 2 to pin 3.
To enable the Platform Flash devices for JTAG configuration, two shunts are installed on
connectors P38/P20, connecting from pin 1 to pin 2 for the first shunt, and connecting pin
3 and 4 for the second shunt. To bypass the Platform Flash devices, a single shunt on
P38/P20 is connected from pin 2 to pin 3. The default board configuration enables all four
devices in the JTAG scan chain.
The ML555 board provides a JTAG connector (P5) to configure the FPGA and program
JTAG devices located in the JTAG chain.
JTAG connector. The JTAG cable connects to P5, and the connector on the ML555 board
has a keyed, plastic shroud to ensure that the device programming cable connects
properly.
FPGA
U10
TDO
TDI
TMS
TCK
CPLD
Figure 4-3: JTAG Chain
U6
TDO
www.xilinx.com
Figure 4-4: JTAG Cable Hook-up
2
P39
4
3
1
Connector
1
3
5
7
9
11
13
JTAG
2 mm
P5
TMS
TCK
Platform Flash
TDI
Figure 4-4
10
12
14
2
4
6
8
U1
#1
TDO
UG201_c4_04_070306
2.5V
shows the pin assignments for the
Virtex-5 FPGA ML555 Development Kit
TMS
TCK
TDO
TDI
2
P38
4
3
1
UG201 (v1.4) March 10, 2008
TMS
TCK
Platform Flash
TDI
U15
#2
TDO
UG201_c4_03_070706
2
P20
4
3
1
R