HW-V5-PCIE2-UNI-G Xilinx Inc, HW-V5-PCIE2-UNI-G Datasheet - Page 32

• Manufacturer Part Number: HW-V5-PCIE2-UNI-G
• Description: KIT DEV PCIEXPRESS GTX VIRTEX5
• Manufacturer: Xilinx Inc
• Series: Virtex™ -5r
• Type: FPGAr

Specifications of HW-V5-PCIE2-UNI-G

• Contents: Board, CD
• For Use With/related Products: Virtex™-5 FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 3: Hardware Description
Table 3-4: P1 PCI Edge Connector Pinout (Continued)
32
Notes:
1. PCI interface signals are connected to FPGA banks 11, 13, and 15. The reference voltage (V
2. NC = no connect.
3. PCIBUSCLK1 is routed to FPGA global clock input pin J14, and PCIBUSCLK2 is routed to FPGA regional clock input pin L34. See
P1 A
Side
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
A83
A84
A85
A86
A87
A88
A89
A90
A91
A92
A93
A94
ML555 board schematics on the CD-ROM for additional information.
“Clock Generation,” page 52
EDGE_CBE5
VCC3V3
EDGE_PAR64
EDGE_AD62
GND
EDGE_AD60
EDGE_AD58
GND
EDGE_AD56
EDGE_AD54
VCC3V3
EDGE_AD52
EDGE_AD50
GND
EDGE_AD48
EDGE_AD46
GND
EDGE_AD44
EDGE_AD42
VCC3V3
EDGE_AD40
EDGE_AD38
GND
EDGE_AD36
EDGE_AD34
GND
EDGE_AD32
unused
GND
unused
Signal
for information on how the PCI bus clock is connected on the ML555 board.
FPGA Pin
AA33
AD34
AB32
AB33
AE33
AE34
AJ34
W32
M33
N32
U31
V33
V34
P34
R34
R32
T34
Y34
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
(1)
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
FPGA
I/O
www.xilinx.com
P1 B
Side
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82
B83
B84
B85
B86
B87
B88
B89
B90
B91
B92
B93
B94
EDGE_CBE6
EDGE_CBE4
GND
EDGE_AD63
EDGE_AD61
VCC3V3
EDGE_AD59
EDGE_AD57
GND
EDGE_AD55
EDGE_AD53
GND
EDGE_AD51
EDGE_AD49
VCC3V3
EDGE_AD47
EDGE_AD45
GND
EDGE_AD43
EDGE_AD41
GND
EDGE_AD39
EDGE_AD37
VCC3V3
EDGE_AD35
EDGE_AD33
GND
unused
unused
GND
Signal
Virtex-5 FPGA ML555 Development Kit
CCO
) for these FPGA banks is 3.0V. See the
UG201 (v1.4) March 10, 2008
FPGA Pin
AA34
AH34
AC34
AC32
AC33
AF33
AF34
M32
W34
N34
U33
R33
U32
V32
Y33
Y32
P32
T33
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
(1)
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
FPGA
I/O
R