HW-V5-PCIE2-UNI-G Xilinx Inc, HW-V5-PCIE2-UNI-G Datasheet - Page 3

• Manufacturer Part Number: HW-V5-PCIE2-UNI-G
• Description: KIT DEV PCIEXPRESS GTX VIRTEX5
• Manufacturer: Xilinx Inc
• Series: Virtex™ -5r
• Type: FPGAr

Specifications of HW-V5-PCIE2-UNI-G

• Contents: Board, CD
• For Use With/related Products: Virtex™-5 FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UG201 (v1.4) March 10, 2008
02/27/07
06/18/07
Date
Version
1.2
1.3
Changed document title and updated
FPGA device speed grade as "-1C ES". Updated
Power,” page
PCI™ Edge Connector pinout. Updated
reference DDR2 reference design included with kit. Added lane assignments to
Table 3-20, page
circuits on
board into 16-lane add-in card connector. Updated
reference designs pre-loaded into ML555 Platform Flash devices. Add Note 3 to
Table 4-1, page
Selection”
System Reference Guide for PROMGen and BitGen software applications. Updated
“Specifying the Xilinx PROM Device”
Figure 4-14
Updated
IP cores. Revised
number. Added footnote 3 to
Figure 3-9, page 56
FPGA output and labeled the Clock MUX inputs. Defined the SATA_MGT_CLKSEL
default selection in
footnote 6 in
indicate pressing and releasing of SW9 and SW11 to parallel load clock synthesizers after
power on to guarantee clock frequency. Updated
page
Reconfiguration,” page 98
page 101
figures
81. Added footnote 1 to
(Figure 4-11, page 105
Table 1-1, page 14
to include process steps and screen shots from ISE 9.1i. Inserted two new
including
page
and
Table 3-20, page
19. Corrected board reference designator for
89; Slave SelectMAP not supported. Updated
60. Updated
Figure
58. Added link to www.idt.com for availability of clock jitter attenuator
Serial Bus Development
to include a 4.7KΩ pull-up resistor on the SATA_MGT_CLKSEL
Table 3-19, page 57
www.xilinx.com
Table 4-7
4-15.
and
to clarify version and build information for PCI and PCI-X
Table 3-33, page 80
Table 3-3, page
Table 4-5, page
58. Updated
and
and
“Platform Flash Image Generation and Programming,”
Figure 4-12, page
Figure
“Additional Documentation,” page
including
Revision
for FPGA output H15. Added additional text to
“DDR2 SDRAM SODIMM,” page 34
4-8. Added reference to the Development
section. Removed "ES" from FPGA part
“Parallel Mode Operation,” page 62
95. Updated
27. Updated
“Initial Board Checks Before Applying
to include ML555 support for plugging
Figure 4-10
Virtex-5 FPGA ML555 Development Kit
Figure 3-14, page 76
Table 3-37, page 86
105).
Table 3-4, page 30
“Generic Dynamic
Figure 3-8, page 55
and
“SelectMAP Clock
Figure
and
to include
4-13. Added
7. Specified
Table 3-34,
to use P1 as
and
to
to