HW-V5-PCIE2-UNI-G Xilinx Inc, HW-V5-PCIE2-UNI-G Datasheet - Page 43

• Manufacturer Part Number: HW-V5-PCIE2-UNI-G
• Description: KIT DEV PCIEXPRESS GTX VIRTEX5
• Manufacturer: Xilinx Inc
• Series: Virtex™ -5r
• Type: FPGAr

Specifications of HW-V5-PCIE2-UNI-G

• Contents: Board, CD
• For Use With/related Products: Virtex™-5 FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 3-11: Ethernet PHY Daughtercard J16 Connection
Virtex-5 FPGA ML555 Development Kit
UG201 (v1.4) March 10, 2008
Notes:
1. These signals are connected to FPGA banks 12 and 20. The bank reference voltage, V
2. NC = no connect.
3. These clocks are connected to FPGA clock-capable I/O pins.
4. These clocks are connected to FPGA global clock pins.
on the CD-ROM for additional information.
J16-EVEN
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
2
4
6
8
R
Signal
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
J16-ODD
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
11
1
3
5
7
9
www.xilinx.com
P1_RXC_RXCLK
P0_RXC_RXCLK
P1_RXCTL_RXDV
P0_RXCTL_RXDV
P1_RD_RXD1
P1_RD_RXD0
P1_RD_RXD2
P1_RD_RXD3
P0_RD_RXD0
P0_RD_RXD1
P0_RD_RXD2
P0_RD_RXD3
P1_RCLK1
P0_RCLK1
No connect
No connect
No connect
No connect
No connect
No connect
P1_RXER
P1_RXD7
P1_RXD4
P1_RXD5
P1_RXD6
P0_RXD4
P0_RXD5
P0_RXD6
P0_RXD7
P0_RXER
P1_CRS
P0_CRS
Signal
(4)
(4)
(3)
(3)
CCO
Ethernet PHY Daughtercard Support
, is 2.5V. See the ML555 board schematics
FPGA Pin
M10
H14
K18
G11
G12
E11
T10
R11
M6
M7
J10
H5
N8
H7
G6
R9
K6
R8
E6
T9
F5
P5
L5
P6
J6
J5
(1)
NC
NC
NC
NC
NC
NC
(2)
FPGA In/Out
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
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