HW-V5-PCIE2-UNI-G Xilinx Inc, HW-V5-PCIE2-UNI-G Datasheet - Page 33

• Manufacturer Part Number: HW-V5-PCIE2-UNI-G
• Description: KIT DEV PCIEXPRESS GTX VIRTEX5
• Manufacturer: Xilinx Inc
• Series: Virtex™ -5r
• Type: FPGAr

Specifications of HW-V5-PCIE2-UNI-G

• Contents: Board, CD
• For Use With/related Products: Virtex™-5 FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Virtex-5 FPGA ML555 Development Kit
UG201 (v1.4) March 10, 2008
ML555 Configuration Headers for PCI Operation
R
M66EN - 66 MHz Enable (Connector P9)
PME# - Power Management Event (Connector P7)
PCIXCAP - PCI-X Capability (Connector P8)
Reference Designs for PCI and PCI-X Operation
The PCI bus on the board schematics has signal names of the form EDGE_<signal name>
(denoting the card edge connector signals). The signal names listed in the A Side and B
Side columns of
The ML555 board supports both PCI and PCI-X applications. The edge connector
interfaces with the system board connector. Xilinx has LogiCORE solutions available for
both PCI and PCI-X designs to facilitate getting started with the application-specific
design. When installing the ML555 board in a PCI or PCI-X add-in card slot, the PCI
Express bracket must be removed from the ML555 board prior to plugging into the system.
The connectors on the ML555 board are oriented for PCI Express operation. When using a
PCI system, the motherboard should be removed from the system chassis as the I/O on the
ML555 board is not oriented to escape out the back of the system unit frame.
P1.B49 is wired to two-pin header pin P9.1. With the P9 jumper shunt removed, M66EN
has a 0.01 μF capacitor to GND. Placing the jumper shunt across pins 1 and 2 of P9 shorts
M66EN to GND.
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P1.A19 is wired to a two-pin header pin P7.1. PME# is pulled up on the system board. P7.2
is wired to U10 pin L30, allowing the FPGA to drive or sense the PME# signal when a
jumper shunt is placed across pins 1 and 2 of P7. The LogiCORE User Guide for PCI/PCI-X
can be consulted for more information on proper use of PME#. By default the PME# signal
is not connected from the system board to the FPGA, meaning the system boards sees only
the pull-up resistor, and the FPGA input is not connected to the system board signal.
P1.B38 is wired to 3-pin header P8 (center pin), and PCIXCAP is connected to FPGA pin
E31.
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The included FPGA bitstreams are example implementations of the PCI32 v4.1 and PCI-X
v6.1 LogiCORE solutions. In these example implementations, the cores are configured to
provide one PCI I/O Space Base Address Register (BAR) and one Memory Space BAR. The
example application on the user interface in these PCI implementations is the same as
M66EN = GND indicates 0 to 33 MHz operation.
M66EN = open indicates 33 MHz to 66 MHz operation. (M66EN is pulled up on the
system board.)
P8.1 is wired to GND through a 10 KΩ pulldown resistor.
P8.2 is wired to P1.B38 and a 0.01μF capacitor to GND.
P8.3 is wired to GND.
A jumper shunt across P8 pins 1 and 2 indicates that the card is PCI-X 66 capable.
No jumper shunt across P8 indicates that the card is PCI-X 133 capable.
A jumper shunt across P8 pins 2 and 3 indicates that the card is not PCI-X capable (i.e.,
it is PCI capable and not PCI-X capable).
Table 3-4
www.xilinx.com
and
Table 3-1, page 24
64-bit Edge Connector for PCI Operation
are standard PCI signal names.
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