HW-V5-PCIE2-UNI-G Xilinx Inc, HW-V5-PCIE2-UNI-G Datasheet - Page 57

• Manufacturer Part Number: HW-V5-PCIE2-UNI-G
• Description: KIT DEV PCIEXPRESS GTX VIRTEX5
• Manufacturer: Xilinx Inc
• Series: Virtex™ -5r
• Type: FPGAr

Specifications of HW-V5-PCIE2-UNI-G

• Contents: Board, CD
• For Use With/related Products: Virtex™-5 FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 3-19: FPGA Global Clock Inputs
Virtex-5 FPGA ML555 Development Kit
UG201 (v1.4) March 10, 2008
FPGA Pins
H15
J20
J21
J16
J17
H18
H17
H19
H20
H14
K17
G16
G15
L18
L19
J19
J14
(4)
(4)
(2)
(2)
(4)
Global Clock Inputs
R
LVPECL_200M_N
LVPECL_200M_P
LVDSCLKMOD1_P
LVDSCLKMOD1_N
SATA_MGT_GCLKP
SATA_MGT_GCLKN
SFP_MGT_GCLKN
SFP_MGT_GCLKP
FPGA_GCLK_30MHZ
P0_RCLK1
P1_RCLK1
PCIBUSCLK2
PCIE_GCLK_P
PCIE_GCLK_N
SATA_MGT_CLKSEL
SMA_GCLKN
SMA_GCLKP
Signal Name
Global clock inputs to the FPGA are summarized in
connected to FPGA bank 3.
(3)
(3)
(3)
(2,5)
(2,5)
(3)
200 MHz LVPECL oscillator Y3
200 MHz LVPECL oscillator Y3
SMA Connector J11
SMA Connector J10
Clock Synthesizer 1
Clock Synthesizer 1
Selectable: 125 MHz Oscillator or Clock Synthesizer 2
Selectable: 125 MHz Oscillator or Clock Synthesizer 2
125 MHz LVDS Oscillator
125 MHz LVDS Oscillator
30 MHz Oscillator
Port 0 Ethernet PHY Receive Clock (if the EPHY daughtercard is installed)
Port 1 Ethernet PHY Receive Clock (if the EPHY daughtercard is installed)
P1-B16 active only when the ML555 board is installed in a PCI bus
connector. Not active when the ML555 board is installed in a PCI Express
connector.
Global clock input available only if an ICS874003-02 PCI Express clock jitter
attenuator circuit is installed on the ML555 board at location U16 (not the
default board configuration). This clock is 100, 125, or 250 MHz as selected
by the CPLD controls. The default is a 250 MHz spread spectrum clock
generated from the add-in card PCI Express input clock on connector P13.
Global clock input available only if an ICS874003-02 PCI Express clock jitter
attenuator circuit is installed on the ML555 board at location U16 (this is not
the default board configuration). This clock is 100, 125, or 250 MHz as
selected by the CPLD controls. The default is a 250 MHz spread spectrum
clock generated from the add-in card input clock for PCI Express operation
on connector P13.
FPGA output used to select the fixed 125 MHz oscillator or the Clock
Synthesizer 2 output to be routed to GTP_DUAL tile X0Y5 MGTREFCLK
and SMA_MGT_GCLK global clock inputs. The ML555 board has a 4.7KΩ
pull-up resistor to 2.5V to provide default selection of clock synthesizer 2 as
the output of the Clock Mux block shown in
www.xilinx.com
(3)
Clock Source
Table
3-19. Global clocks are
Figure 3-8
and
Clock Generation
Figure
3-9.
57