HW-V5-PCIE2-UNI-G Xilinx Inc, HW-V5-PCIE2-UNI-G Datasheet - Page 66

• Manufacturer Part Number: HW-V5-PCIE2-UNI-G
• Description: KIT DEV PCIEXPRESS GTX VIRTEX5
• Manufacturer: Xilinx Inc
• Series: Virtex™ -5r
• Type: FPGAr

Specifications of HW-V5-PCIE2-UNI-G

• Contents: Board, CD
• For Use With/related Products: Virtex™-5 FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 3: Hardware Description
Table 3-23: Clock Synthesizer 2 Frequency Output for Multiplier/Divider Values with a 25 MHz Input Clock
66
M8
Multiplier Input
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Selection
(hex)
0x1D – 0xFF
0x00 – 0x09
0x00 – 0xFF
M[7:0]
0A
0D
1A
0B
0C
0E
1B
1C
0F
10
12
13
14
15
16
17
18
19
11
Frequency Range
Table 3-23
M and divisor N inputs to the ICS8442 device with a 25 MHz reference clock input for
Clock Synthesizer 2.
Will not LOCK
Will not LOCK
VCO Lock
(MHz)
250
275
300
325
350
375
400
425
450
475
500
525
550
575
600
625
650
675
700
shows the clock synthesis ranges possible with different selections of multiplier
(MHz) with Divisor =
Output Frequency
1 N[1:0]=00b
www.xilinx.com
N/A
N/A
250
275
300
325
350
375
400
425
450
475
500
525
550
575
600
625
650
675
700
Frequency (MHz)
with Divisor = 2
N[1:0]=01b
Output
N/A
137.5
162.5
187.5
212.5
237.5
262.5
287.5
312.5
337.5
N/A
125
150
175
200
225
250
275
300
325
350
Virtex-5 FPGA ML555 Development Kit
Divisor = 4
N[1:0]=10b
Frequency
(MHz) with
Output
106.25
131.25
143.75
156.25
168.75
118.75
UG201 (v1.4) March 10, 2008
N/A
68.75
81.25
93.75
112.5
137.5
162.5
N/A
62.5
87.5
100
125
150
175
75
Frequency
Divisor = 8
N[1:0]=11b
(MHz) with
Output
34.375
40.625
46.875
53.125
59.375
65.625
71.875
78.125
84.375
N/A
31.25
43.75
56.25
68.75
81.25
N/A
37.5
62.5
87.5
50
75
R