HW-V5-PCIE2-UNI-G Xilinx Inc, HW-V5-PCIE2-UNI-G Datasheet - Page 87
HW-V5-PCIE2-UNI-G
Manufacturer Part Number
HW-V5-PCIE2-UNI-G
Description
KIT DEV PCIEXPRESS GTX VIRTEX5
Manufacturer
Xilinx Inc
Series
Virtex™ -5r
Type
FPGAr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.HW-V5-PCIE2-UNI-G.pdf
(108 pages)
Specifications of HW-V5-PCIE2-UNI-G
Contents
Board, CD
For Use With/related Products
Virtex™-5 FPGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- XC5VLX30-1FFG324C PDF datasheet
- XC5VLX30-1FFG324C PDF datasheet #2
- HW-V5-PCIE2-UNI-G PDF datasheet #3
- Current page: 87 of 108
- Download datasheet (4Mb)
Configuration
Virtex-5 FPGA ML555 Development Kit
UG201 (v1.4) March 10, 2008
R
The Virtex-5 FPGA ML555 board includes several options to configure the XC5VLX50T
FPGA, XC2C32 CoolRunner-II CPLD, and the XCF32PF Platform Flash. The basic
configuration modes for the Virtex-5 family are:
•
•
•
•
•
The CPLD and Platform Flash can only be configured via JTAG. The Platform Flash
contains up to four unique bitstreams for programming the FPGA. The unique
combination of the FPGA connected to the Platform Flash through the CPLD allows for
static and dynamic bitstream selection of the FPGA via Slave and Master SelectMAP
modes.
This chapter provides a description of the FPGA configuration circuitry and methods used
on the Virtex-5 FPGA ML555 board. The JTAG chain permits the CPLD and/or the
Platform Flash devices to be bypassed with onboard headers.
location of configuration switches, connectors, and devices discussed in this chapter.
JTAG mode via Parallel Cable IV, Platform Cable USB, or equivalent
Master SelectMAP mode via CPLD and Platform Flash
Slave SelectMAP mode via CPLD and Platform Flash
Slave Serial mode via CPLD and Platform Flash
Master Serial mode via CPLD and Platform Flash
www.xilinx.com
Figure 4-1
Chapter 4
shows the
87
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