HW-V5-PCIE2-UNI-G Xilinx Inc, HW-V5-PCIE2-UNI-G Datasheet - Page 52

• Manufacturer Part Number: HW-V5-PCIE2-UNI-G
• Description: KIT DEV PCIEXPRESS GTX VIRTEX5
• Manufacturer: Xilinx Inc
• Series: Virtex™ -5r
• Type: FPGAr

Specifications of HW-V5-PCIE2-UNI-G

• Contents: Board, CD
• For Use With/related Products: Virtex™-5 FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 3: Hardware Description
Clock Generation
52
be configured as a serial COM port for the user to continue working with serial
communication utilities like HyperTerminal or Tera Term Pro.
The CP210x USB-to-UART Bridge VCP drivers can be downloaded from the Silicon
Laboratories website at:
For technical information and support for the CP210x USB-to-UART bridge controller
integrated circuit and the associated VCP device driver, visit the Silicon Laboratories
website at www.silabs.com.
The ML555 FPGA must have a UART design instantiated to communicate with the PC on
the USB interface. A reference design and/or bit image is included on the CD ROM to
permit testing the FPGA to VCP interface. The reference design utilizes the MicroBlaze soft
processor and a UART core to communicate to the PC terminal window.
The ML555 board provides a USB Type-B device port connector that is intended to be
cabled to the host computer with a USB Type-A port connector.
Table 3-17
Table 3-17: USB Connector Signal Names and Pin Assignments
The clock generation section of the ML555 board provides three fixed, two programmable,
and two pairs of differential SMA inputs for clock sources:
1.
2.
3.
One pair of SMA clock inputs is connected to the global clock bank, and the other pair of
SMA clock inputs is connected to the GTP_DUAL tile X0Y3 MGTREFCLK inputs. The
global clock SMA ports can also be used as an output port to route internal debug signals
for triggering or viewing on an oscilloscope. Consult the Virtex-5 FPGA User Guide for
additional information on clocking and the appropriate I/O standards for high-speed
clock and data signals.
Connector
(J1) Pin
http://www.silabs.com/tgwWebApp/public/web_content/products/
Microcontrollers/en/MCU_Downloads.htm
Epson EG-2121CA-125.0000M-LHPAB 2.5V LVDS (differential) oscillator
125 MHz FPGA oscillator for Gigabit Ethernet
Epson SG-8002CA-30.0000M-PCC 3.3V LVCMOS (single-ended) oscillator
This clock is buffered via U9. It goes to the CPLD and one of the FPGA global clock
inputs.
Epson EG-2121CA-200.0000M-PHPAB 2.5V LVPECL (differential) oscillator
USB
1
2
3
4
describes the USB interface pin assignments.
VBUS
USB_DATA_N
USB_DATA_P
GROUND
Signal Name
www.xilinx.com
+5V from HOST system (not used)
Bidirectional differential serial data (n-side)
Bidirectional differential serial data (p-side)
Signal ground
Virtex-5 FPGA ML555 Development Kit
Description
UG201 (v1.4) March 10, 2008
R