HW-V5-PCIE2-UNI-G Xilinx Inc, HW-V5-PCIE2-UNI-G Datasheet - Page 74

• Manufacturer Part Number: HW-V5-PCIE2-UNI-G
• Description: KIT DEV PCIEXPRESS GTX VIRTEX5
• Manufacturer: Xilinx Inc
• Series: Virtex™ -5r
• Type: FPGAr

Specifications of HW-V5-PCIE2-UNI-G

• Contents: Board, CD
• For Use With/related Products: Virtex™-5 FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 3: Hardware Description
User Pushbutton Switches
Pushbutton Program Switch (SW6)
Pushbutton Reset Switch (SW7)
Power Consumption
74
The ML555 board provides three user pushbutton switches. The switch outputs are pulled
up to 2.5V using 4.7 KΩ resistors on the board. The pushbuttons generate a switch closure
to GND when pressed. Switch contact debounce logic must be implemented inside the
FPGA.
Table 3-29: User Pushbutton Switch Assignments
The ML555 board provides a pushbutton program switch for initiating reconfiguration of
the Virtex-5 FPGA. A CPLD image is provided with the ML555 board to enable pressing
and releasing the program pushbutton switch (SW6) to initiate a full FPGA device
configuration cycle while the board is powered on. The CPLD design files and bit image
are on the reference CD included in the kit. Pressing this switch causes the FPGA to clear
its internal configuration memory and then load the currently selected image (via the P3
image select jumper block) from the Platform Flash (U1 and U15). See
for additional information on P3 selection of stored FPGA bitstream images.
The ML555 board provides a pushbutton switch SW7 for a user-assigned function. This
switch, labelled RESET, is wired to the CPLD U6 pin 18 (general-purpose I/O pin). The
switch output is connected by a 4.7 KΩ pull-up resistor to 2.5V. This pushbutton generates
a switch closure to GND when pressed. Switch contact debounce logic must be
implemented inside the CPLD. There are multiple connections between the CPLD U6 and
the FPGA U10 to transmit SW7 activity.
The PCI specification outlines the power consumption limitations for PCI add-in boards.
The maximum allowable power consumption across all power rails (+5V, +3.3V, +12V,
-12V) is 25W.
On the PCI connector two signals allow the power demand of a board to be specified.
The PRSNT[1:2]# signals are used by a system board to detect if an add-in card is
physically present in the slot and the total power requirements of the add-in card. The
signals are required for the add-in card but are optional for the system board. The ML555
board uses the EDGE_PRSNT1# and EDGE_PRSNT2# signals to request the maximum
25W power limit by grounding PRSNT1# and leaving PRSNT2# open. The
SKT_PRSNT[1:2]# signals on the PCI-X expansion socket (J1) are routed to the FPGA for
sensing.
Notes:
1. These signals are connected to FPGA bank 2. The FPGA reference voltage, V
USER_SW0
USER_SW1
USER_SW2
See the ML555 board schematics on the CD-ROM for additional information.
Pushbutton Switch Signal
Table 3-29
lists the FPGA pin assignments.
www.xilinx.com
USER1 SW1
USER2 SW2
USER3 SW3
Description
Virtex-5 FPGA ML555 Development Kit
AF21
AF20
AF14
UG201 (v1.4) March 10, 2008
FPGA Pin Number
(FF1136 Package)
CCO
Table 4-6, page 98
, for this bank is 2.5V.
(1)
R