HW-V5-PCIE2-UNI-G Xilinx Inc, HW-V5-PCIE2-UNI-G Datasheet - Page 95

• Manufacturer Part Number: HW-V5-PCIE2-UNI-G
• Description: KIT DEV PCIEXPRESS GTX VIRTEX5
• Manufacturer: Xilinx Inc
• Series: Virtex™ -5r
• Type: FPGAr

Specifications of HW-V5-PCIE2-UNI-G

• Contents: Board, CD
• For Use With/related Products: Virtex™-5 FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 4-4: CPLD Pin Listing (Continued)
Table 4-5: Pin Listing for Platform Flash
Virtex-5 FPGA ML555 Development Kit
UG201 (v1.4) March 10, 2008
Notes:
1. The Net Names and Directions for pins 29 through 33 were chosen to support a specific PCI/PCI-X design as described in
2. All CPLD I/O are 2.5V LVCMOS.
Number
Number
Pin
Programming Examples.”
Pin
G1
D1
H6
C1
B4
B3
C2
32
33
34
35
36
37
38
39
40
41
42
43
44
BUSY_TO_FLASH_B
CPLD_TDO
FLASH_CE_B (U1) or
FLASH_CE1_B (U15)
FLASH_CF_B
FLASH_CLKIN
FLASH_CLKOUT
FLASH_D0
RTR
PCIW_EN
FPGA_RDWR_B
VCC2V5
CPLD_SPARE3
PCIE_RST
FLASH_CE1_B
FLASH_REV_SEL0
FLASH_REV_SEL1
BUSY_TO_FLASH_B
FLASH_CE_B
FLASH_CF_B
FLASH_OE_RESET_B
R
(1)
Net Name
Net Name
(1)
The user can use these pins as spare, bidirectional pins.
Direction
O
O
Direction
I
I
I
I
I
I/O
O
O
O
O
O
O
O
O
I
I
I
I
www.xilinx.com
CLKOUT
Pin Type
BUSY
CLK
TDI
IO/GOE2
IO/GOE3
IO/GOE4
Pin Type
CE
CF
D0
IO/GC2
IO/GC3
VAUX
IO18
IO19
IO20
IO21
IO22
IO23
IO24
Active-Low Busy signal connected from CPLD Pin
41
JTAG TDI connected from CPLD JTAG TDO
Active-Low Chip Enable connected from CPLD Pin
42 (U1) or CPLD Pin 38 (U15)
Active-Low Configuration Pulse input connected to
CPLD Pin 43
Clock Input connected from Pin 1 of Header P2
Clock Output connected to Pin 5 of Header P2
SelectMAP data bit 0 connected to FPGA
Input connected from Pin F16 of FPGA
Input connected from Pin F11 of FPGA
Output connected to RDWR_B pin of FPGA
2.5V auxiliary power
Spare I/O connected to FPGA pin H9
Active-Low RESET input for PCI Express from
P13-A11
Output connected to the CE pin of Platform Flash
U15
Output connected to the REV_SEL0 pin of
Platform Flash devices
Output connected to the REV_SEL1 pin of
Platform Flash devices
Output connected to the BUSY pin of Platform
Flash devices
Output connected to the CE pin of Platform Flash
U1
Output connected to the CF pin of Platform Flash
devices
Output connected to the OE/RESET pin of
Platform Flash devices
Description
Description
SelectMAP Interface
“CPLD
95