HW-V5-PCIE2-UNI-G Xilinx Inc, HW-V5-PCIE2-UNI-G Datasheet - Page 60

• Manufacturer Part Number: HW-V5-PCIE2-UNI-G
• Description: KIT DEV PCIEXPRESS GTX VIRTEX5
• Manufacturer: Xilinx Inc
• Series: Virtex™ -5r
• Type: FPGAr

Specifications of HW-V5-PCIE2-UNI-G

• Contents: Board, CD
• For Use With/related Products: Virtex™-5 FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 3: Hardware Description
60
Serial Bus Clocking with Optional ICS874003-02 Clock Jitter Attenuator
(PCI Express Operation)
By default, the ML555 board connects the PCIE_REFCLK input from the add-in card
connector, through two DC blocking capacitors, and then to GTP X0Y2 MGTREFCLK pins
Y4 and Y3.
The ML555 board layout accommodates end-user installation of an ICS874003-02 PCI
Express Clock Jitter attenuator module as shown in
installed in board location U16, and series resistors R450 and R451 need to be removed
from the board assembly. Contact Integrated Devices Technology (IDT) for information
and availability of clock jitter attenuator circuits at www.idt.com.
The PCI Express system clock is an ICS874003-02 clock jitter attenuator circuit. The ICS
device has dual LVDS outputs, one of which is connected to GTP_DUAL tile X0Y2
MGTREFCLK and the other is connected to FPGA global clock input pins J16 and J17. The
jitter attenuator can generate either a 100 MHz or a 250 MHz reference clock for the GTP
transceiver and clock management tile (CMT) within the FPGA.
Figure 3-10
and then to the FPGA. The CPLD image provided with the ML555 board by default selects
a 250 MHz reference clock to be generated by the ICS874003-02. Spare I/O from the FPGA
to CPLD could be used to dynamically select different GTP reference clocks to be
generated by the jitter attentuator circuit. Source code for the CPLD design provided with
the ML555 board is included on the CD-ROM.
Spread spectrum clocking is supported by routing the system board clock into the
transceiver and then generating a local clock for the FPGA design. The external clock from
one GTP_DUAL tile can be used to drive the CLKIN ports of neighboring tiles. A
GTP_DUAL tile shares its clock with its neighbors using dedicated internal clock routing
resources. Refer to the Virtex-5 FPGA RocketIO GTP Transceiver User Guide for additional
information on clocking resources.
P13-A13
P13-A14
shows the connections from the PCI Express connector to the jitter attenuator
PCIE_REFCLK
Figure 3-10: PCI Express Clocking and Control
www.xilinx.com
874003-02
Clock Jitter
Attenuator
(U16)
ICS
CPLD
nA0
nA1
A0
A1
PCIE250M_P
PCIE250M_N
PCIE_GCLK_P
PCIE_GCLK_N
CPLD_SPARE3
CPLD_SPARE2
CPLD_SPARE1
Figure
Virtex-5 FPGA ML555 Development Kit
J16
J17
Y4
Y3
3-10. The ICS device should be
MGT_REFCLKP
MGT_REFCLKN
GCLKP
GCLKN
UG201 (v1.4) March 10, 2008
U10 FPGA
UG201_c3_09_121006
GTP X0Y2
R