HW-V5-PCIE2-UNI-G Xilinx Inc, HW-V5-PCIE2-UNI-G Datasheet - Page 99

• Manufacturer Part Number: HW-V5-PCIE2-UNI-G
• Description: KIT DEV PCIEXPRESS GTX VIRTEX5
• Manufacturer: Xilinx Inc
• Series: Virtex™ -5r
• Type: FPGAr

Specifications of HW-V5-PCIE2-UNI-G

• Contents: Board, CD
• For Use With/related Products: Virtex™-5 FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Virtex-5 FPGA ML555 Development Kit
UG201 (v1.4) March 10, 2008
From P2
Notes:
1. FORCE, WIDE, PCIW_EN, and RTR are FPGA general-purpose I/Os.
To P2
R
CLKOUT
CLKIN
Platform Flash
XCF32PF
Platform Flash
Figure 4-7: CPLD Configuration for Dynamic Reconfiguration
U1
simply specifies the bitstream revision along with a signal to indicate when to start the
configuration process. Logic within the CPLD then controls the configuration pins to the
FPGA and Platform Flash to complete the configuration cycle. This logic can be as simple
as driving the REV_SEL pins to the Flash and the PROG_B pin on the FPGA to begin
configuration. The MAN_AUTO_B input to the CPLD can be incorporated into the design
to override the dynamic reconfiguration and allow only static configuration as described
in XAPP693
Flash to dynamically reconfigure an FPGA.
The LogiCORE Getting Started Guide for PCI-X provides information on using the FORCE,
WIDE, PCIW_EN, and RTR signals to support dynamic reconfiguration. XAPP938
provides an example of dynamic FPGA reconfiguration.
XCF32PF
U15
OE/RESET
REV_SEL0
REV_SEL1
CE1 (U15)
CE (U1)
1
3
5
BUSY
D[0:7]
P3
CF
[Ref
2
4
6
12]. This application note provides details on using a CPLD and Platform
www.xilinx.com
43
44
39
40
36
42
41
12 8 2
State Machine
and Logic
XC2C32
CPLD
U6
3 13
8
Figure 4-7
2
1
31
29
33
32
34
23
28
27
30 MHz
5
6
CPLD
CLK
10
illustrates this method.
DIP SW
From/To P2
SW5
D[7:0]
FORCE
WIDE
PCIW_EN
RTR
DONE
DOUT_BUSY
RDWR_B
CS_B
PROG_B
INIT_B
CPLD_SPARE[1:10]
CCLK
(1)
SelectMAP Interface
(1)
XC5VLX50T
(1)
(1)
FPGA
U10
M0 M1 M2
UG201_c4_07_022608
[Ref 4]
99