HW-V5-PCIE2-UNI-G Xilinx Inc, HW-V5-PCIE2-UNI-G Datasheet - Page 97

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HW-V5-PCIE2-UNI-G

Manufacturer Part Number
HW-V5-PCIE2-UNI-G
Description
KIT DEV PCIEXPRESS GTX VIRTEX5
Manufacturer
Xilinx Inc
Series
Virtex™ -5r
Type
FPGAr

Specifications of HW-V5-PCIE2-UNI-G

Contents
Board, CD
For Use With/related Products
Virtex™-5 FPGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Part Number:
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Table 4-5: Pin Listing for Platform Flash (Continued)
Virtex-5 FPGA ML555 Development Kit
UG201 (v1.4) March 10, 2008
Notes:
1. The ML555 board uses 2.5V I/O drivers for the JTAG chain. The Platform Flash V
Number
Pin
of devices in the chain.
D2
D3
D4
G2
E3
E4
F2
F3
F4
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
CPLD Programming Examples
R
Net Name
Static Configuration
Figure 4-6
the FPGA to be statically selected and programmed with up to four bitstreams located in
the Flash. The selection of the bitstream is based on the configuration of the Flash Image
Select header P3.
shows one possibility of connecting the FPGA to the Flash. This example allows
Direction
O
Table 4-6
I
I
I
I
I
I
I
I
www.xilinx.com
Pin Type
shows the jumper settings for header P3.
DNC10
DNC11
DNC4
DNC5
DNC6
DNC7
DNC8
DNC9
CEO
Do Not Connect
Do Not Connect
Do Not Connect
Do Not Connect
Do Not Connect
Do Not Connect
Do Not Connect
Do Not Connect
Do Not Connect
CCJ
connection should match JTAG I/O voltages
Description
SelectMAP Interface
97

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