HW-V5-PCIE2-UNI-G Xilinx Inc, HW-V5-PCIE2-UNI-G Datasheet - Page 73

• Manufacturer Part Number: HW-V5-PCIE2-UNI-G
• Description: KIT DEV PCIEXPRESS GTX VIRTEX5
• Manufacturer: Xilinx Inc
• Series: Virtex™ -5r
• Type: FPGAr

Specifications of HW-V5-PCIE2-UNI-G

• Contents: Board, CD
• For Use With/related Products: Virtex™-5 FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

User LEDs
Configuration INIT and DONE LEDs
Virtex-5 FPGA ML555 Development Kit
UG201 (v1.4) March 10, 2008
R
3.
The ML555 board provides three user LEDs that can be turned ON by driving the LED
signals to Ground.
Table 3-27: User LED Pin Assignments
The ML555 board provides INIT and DONE indicator LEDs, that are turned ON by the
FPGA during the configuration process. The FPGA INIT pin (N14) drives the INIT LED
(D5) buffer transistor (Q2). The FPGA DONE pin (M15) drives the DONE LED (D6) buffer
transistor (Q1).
Table 3-28: Configuration INIT and DONE LED Pin Assignments
Notes:
1. These signals are connected to FPGA bank 20. The FPGA reference voltage, V
Notes:
1. These signals are connected to FPGA configuration bank 0. The FPGA reference voltage for this bank
USER_LED0
USER_LED1
USER_LED2
FPGA_INIT
FPGA_DONE
See the ML555 board schematic on the CD-ROM for additional information.
is 2.5V. See the ML555 board schematics on the CD-ROM for additional information.
Using one of the clock synthesizer chips. If using the parallel input mode, SW9 and/or
SW11 must be pressed and released to obtain a known output frequency from the
clock synthesizers after a power-on cycle.
♦
♦
Typically, CLOCK_SYNTH1 is reserved for the DDR2 memory clock generation.
If the DDR2 memory is not used or the clock frequency for the DDR2 memory is
200 MHz, this clock can be used for 200 MHz clock generation. The ML555 board
supports DDR2-400, DDR2-533, and DDR2-667 rates.
CLOCK_SYNTH2 routed through the U3 clock mux goes to GCLK_P J20 and
GCLK_N J21. The SATA_MGT_CLKSEL output port on FPGA pin H15 must be
set to either a logic 1 level to select the Clock Synthesizer 2 as the clock source or a
logic 0 level to select the fixed 125 MHz LVDS clock source as input to the global
clock pins. Depending on which GTP elements are used in the design, the second
clock synthesizer might be available for IDELAYCTRL reference clock.
LED Signal
LED
Table 3-28
Table 3-27
www.xilinx.com
lists the FPGA pin assignments.
lists the FPGA pin assignments.
USER1 D1
USER2 D2
USER3 D3
D5 INIT
D6 DONE
Designation
Designation
H8
G8
G10
N14
M15
FPGA Pin Number
FPGA Pin Number
(FF1136 Package)
(FF1136 Package)
CCO
, for this bank is 2.5V.
User LEDs
(1)
(1)
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