EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 302

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Contents
Section VI. System Configuration & Upgrades
Chapter 11. Configuring Stratix & Stratix GX Devices
Chapter 12. Remote System Configuration with Stratix & Stratix GX Devices
x
Conclusion .......................................................................................................................................... 10–32
Revision History .................................................................................................................... Section VI–2
Introduction .......................................................................................................................................... 11–1
Device Configuration Overview ....................................................................................................... 11–2
Configuration File Size ....................................................................................................................... 11–6
Altera Configuration Devices ............................................................................................................ 11–7
Configuration Schemes ....................................................................................................................... 11–7
Configuring Using the MicroBlaster Driver .................................................................................. 11–51
Device Configuration Pins ............................................................................................................... 11–51
Introduction .......................................................................................................................................... 12–1
Remote Configuration Operation ...................................................................................................... 12–1
Quartus II Software Support ............................................................................................................ 12–12
Using Enhanced Configuration Devices ........................................................................................ 12–19
Combining MAX Devices & Flash Memory .................................................................................. 12–42
Using an External Processor ............................................................................................................ 12–43
Conclusion .......................................................................................................................................... 12–44
Configuration Speed & Schemes ................................................................................................ 10–30
Remote Update Configuration ................................................................................................... 10–31
JTAG Instruction Support ........................................................................................................... 10–31
MSEL[2..0] Pins ............................................................................................................................... 11–3
V
PORSEL Pins ................................................................................................................................... 11–5
nIO_PULLUP Pins ......................................................................................................................... 11–5
TDO & nCEO Pins .......................................................................................................................... 11–6
PS Configuration ............................................................................................................................ 11–7
FPP Configuration ........................................................................................................................ 11–21
PPA Configuration ....................................................................................................................... 11–30
JTAG Programming & Configuration ....................................................................................... 11–36
JTAG Programming & Configuration of Multiple Devices ................................................... 11–39
Configuration with JRunner Software Driver .......................................................................... 11–41
Jam STAPL Programming & Test Language ............................................................................ 11–42
Remote System Configuration Modes ........................................................................................ 12–3
Remote System Configuration Components .............................................................................. 12–5
altremote_update Megafunction ................................................................................................ 12–14
Remote Update WYSIWYG ATOM ........................................................................................... 12–17
Local Update Programming File Generation ........................................................................... 12–21
Remote Update Programming File Generation ....................................................................... 12–32
CCSEL
Pins ...................................................................................................................................... 11–3
Stratix Device Handbook, Volume 2
Altera Corporation