EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 373

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Altera Corporation
July 2005
M-RAM Blocks
M-RAM blocks support byte enables for the 16, 18, 32, 36, 64, and
byteena signals (byteena_a and byteena_b) combine to form the
necessary 16 byte enables.
selection.
Notes to
(1)
(2)
Table 2–5. Byte Enable for M-RAM Blocks
Table 2–6. M-RAM Combined Byte Selection for 144 Mode (Part 1 of 2),
Notes
72 modes. In the 128 or 144 simple dual-port mode, the two sets of
Any combination of byte enables is possible.
Byte enables can be used in the same manner with 8-bit words, that is, in 16, 32,
and 64 modes.
byteena
[0] = 1
[1] = 1
[2] = 1
[3] = 1
[4] = 1
[5] = 1
[6] = 1
[7] = 1
(1),
TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices
Table
(2)
byteena_a
2–5:
[10] = 1
[11] = 1
[0] = 1
[1] = 1
[2] = 1
[3] = 1
[4] = 1
[5] = 1
[6] = 1
[7] = 1
[8] = 1
[9] = 1
datain 18
[17..9]
[8..0]
Tables 2–5
–
–
–
–
–
–
and
Stratix Device Handbook, Volume 2
Notes
datain 36
2–6
[26..18]
[35..27]
[17..9]
[8..0]
–
–
–
–
summarize the byte
(1),
datain 144
(2)
[107..99]
[26..18]
[35..27]
[44..36]
[53..45]
[62..54]
[71..63]
[80..72]
[89..81]
[98..90]
[17..9]
[8..0]
datain 72
[26..18]
[35..27]
[44..36]
[53..45]
[62..54]
[71..63]
[17..9]
[8..0]
2–5