EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 361

IC STRATIX FPGA 40K LE 956-BGA

EP1S40B956C5

Manufacturer Part Number
EP1S40B956C5
Description
IC STRATIX FPGA 40K LE 956-BGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S40B956C5

Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
683
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
956-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-

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0
Figure 1–23. V
Altera Corporation
July 2005
CCINT
Plane Partitioned for V
Thick V
Because of board constraints, you might not be able to partition a V
island. Instead, run a thick trace from the power supply to each V
The traces should be at least 20 mils thick.
In each of these three cases, you should filter each V
decoupling circuit shown in
high impedance at frequencies of 50 MHz or higher and a 10- F tantalum
parallel capacitor where the power enters the board. Decouple each V
pin with a 0.1- F and 0.001- F parallel combination of ceramic capacitors
located as close as possible to the Stratix or Stratix GX device. You can
connect the GNDA pins directly to the same ground plane as the device’s
digital ground.
CCA
Trace
CCA
Island
General-Purpose PLLs in Stratix & Stratix GX Devices
Figure
1–24. Place a ferrite bead that exhibits
Stratix Device Handbook, Volume 2
CCA
pin with a
CCA
CCA
1–51
pin.
CCA

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