EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 521

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Figure 5–37. Differential HSTL Class II Termination
Altera Corporation
July 2005
Transmitter
Differential
50 Ω
V
TT
Differential SSTL-2 Termination
The SSTL-2 Class I and II I/O standards require a 1.25-V V
1.25-V V
termination for SSTL-2 Class I and II I/O standard.
Figure 5–38. Differential SSTL-2 Class I Termination
= 0.75 V
Transmitter
Differential
TT
50 Ω
V
.
TT
Figures 5–37
= 0.75 V
25 Ω
25 Ω
High-Speed Differential I/O Interfaces in Stratix Devices
Z
Z
0
0
= 50 Ω
= 50 Ω
and
50 Ω
Z
Z
5–38
V
0
0
TT
= 50 Ω
= 50 Ω
= 0.75 V
show the device with differential
50 Ω
V
TT
Stratix Device Handbook, Volume 2
= 1.25 V
50 Ω
V
TT
= 0.75 V
50 Ω
V
TT
= 1.25 V
Differential
Receiver
REF
Differential
Receiver
and a
5–49