EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 729

IC STRATIX FPGA 40K LE 956-BGA

EP1S40B956C5

Manufacturer Part Number
EP1S40B956C5
Description
IC STRATIX FPGA 40K LE 956-BGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S40B956C5

Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
683
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
956-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-

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Figure 11–3. Multi-Device Configuration Circuit
Notes to
(1)
(2)
(3)
(4)
Altera Corporation
July 2005
V CC
GND
N.C.
When performing multi-device active serial configuration, you must generate the configuration device programmer
object file (.pof) from each project’s SOF. You can combine multiple SOFs using the Quartus II software through the
Device & Pin Option dialog box. For more information on how to create configuration and programming files, see
the Software Settings section in the Configuration Handbook, Volume 2.
The pull-up resistor should be connected to the same supply voltage as the configuration device.
The enhanced configuration devices and EPC2 devices have internal programmable pull-ups on OE and nCS. You
should only use the internal pull-ups of the configuration device if the nSTATUS and CONF_DONE signals are pulled
up to 3.3 V or 2.5 V (not 1.8 V or 1.5 V). If external pull-ups are used, they should be 10 k
The nINIT_CONF pin is available on EPC16, EPC8, EPC4, and EPC2 devices. If nINIT_CONF is not used, nCONFIG
must be pulled to V
in EPC16, EPC8, EPC4, and EPC2 devices. These devices do not need an external pull-up resistor on the
nINIT_CONF pin.
Stratix or Stratix GX Device 2
MSEL2
MSEL1
MSEL0
nCEO
Figure
CONF_DONE
11–3:
nCONFIG
nSTATUS
DATA0
DCLK
nCE
CC
through a resistor. The nINIT_CONF pin has an internal pull-up resistor that is always active
After the first Stratix or Stratix GX device completes configuration during
multi-device configuration, its nCEO pin activates the second device’s
nCE pin, prompting the second device to begin configuration. Because all
device CONF_DONE pins are tied together, all devices initialize and enter
user mode at the same time.
In addition, all nSTATUS pins are tied together; thus, if any device
(including the configuration devices) detects an error, configuration stops
for the entire chain. Also, if the first configuration device does not detect
CONF_DONE going high at the end of configuration, it resets the chain by
pulsing its OE pin low for a few microseconds. This low pulse drives the
OE pin low on the second configuration device and drives nSTATUS low
on all Stratix and Stratix GX devices, causing them to enter an error state.
If the Auto-Restart Configuration on Frame Error option is turned on in
the software, the Stratix or Stratix GX device releases its nSTATUS pins
after a reset time-out period. When the nSTATUS pins are released and
pulled high, the configuration devices reconfigure the chain. If the Auto-
V CC
GND
Stratix or Stratix GX Device 1
nCEO
MSEL2
MSEL1
MSEL0
CONF_DONE
Note (1)
nCONFIG
nSTATUS
DATA0
DCLK
nCE
V CC
GND
10 kΩ
(2)
(3)
V CC
10 kΩ
(2)
(4)
Configuring Stratix & Stratix GX Devices
V CC
10 kΩ
(2)
(3)
Stratix Device Handbook, Volume 2
DCLK
DATA
OE
nCS
nINIT_CONF (4)
EPC1/EPC2
(3)
(3)
nCASC
DCLK
DATA
nCS
OE
nINIT_CONF (4)
EPC1/EPC2
11–11

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